AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 19

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

Bit 5: Tx Path Select Profile 1
The AD9879 quadrature digital upconverter is capable of
storing two preconfigured modulation modes called profiles.
Each profile defines a transmit frequency tuning word and cable
driver amplifier gain (DAC gain) setting. The profile select bit
or PROFILE pin programs the current register profile to be
used. The profile select bit should always be 0 if the PROFILE
pin is to be used to switch between profiles. Using the profile
select bit as a means of switching between different profiles
requires the PROFILE pin to be tied low.
REGISTERS 0x10–0x17—CARRIER FREQUENCY
TUNING
Tx Path Frequency Tuning Words
The frequency tuning word (FTW) determines the DDS-
generated carrier frequency (f
concatenation of register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB and Bit 0 is the LSB.
The carrier frequency equation is given as
where:
f
FTW < 0 × 2000000.
Changes to FTW bytes take effect immediately.
Cable Driver Gain Control
The AD9879 has a 3-pin interface to the AD832x family of
programmable gain cable driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9879.
In its default mode, the complete 8-bit register value is
transmitted over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register 0x0F is set high, Bits [7:4] determine the
8-bit word sent over the CA interface according to Table 7.
SYSCLK
fc = [FTW × f
= M × f
OSCIN
.
SYSCLK
]/2
26
C
) and is formed via a
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Table 7. Cable Driver Gain Control
Bits [7:4]
0000
0001
...
0111
1000
In this mode, the lower bits determine the fine gain setting of
the DAC output.
Table 8. DAC Output Fine Gain Setting
Bits [3:0]
0000
0001
...
1110
1111
New data is automatically sent over the 3-wire CA interface
(and DAC gain adjust) whenever the value of the active gain
control register changes or a new profile is selected. The default
value is 0x00 (lowest gain).
The formula for the combined output level calculation of the
AD9879 fine gain and AD8327 or AD8322 coarse gain is
where:
fine is the decimal value of Bits [3:0].
coarse is the decimal value of Bits [7:8].
V
V
V
9879(0)
8327
8322
V
V
is level at output of AD8327 in dBmV.
is level at output of AD8322 in dBmV.
8327
8322
is level at AD9879 output in dBmV for fine = 0.
= V
= V
9879(0)
9879(0)
CA Interface Transmit Word
0000 0000 (default)
0000 0001
...
0100 0000
1000 0000
DAC Fine Gain
0.0 dB (default)
0.5 dB
...
7.0 dB
7.5 dB
+ (fine)/2 + 6(coarse) − 19
+ (fine)/2 + 6(coarse) − 14
AD9879
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