AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 26

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

AD9879
PROGRAMMING THE AD8321/AD8323 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER
GAIN CONTROL
Programming the gain of the AD832x family of cable driver
amplifiers can be accomplished via the AD9879 cable amplifier
control interface. Four 8-bit registers within the AD9879 (one
per profile) store the gain value to be written to the serial 3-wire
port. Typically, either the AD8321/AD8323 or AD8322/AD8327
variable gain cable amplifiers are connected to the chip’s 3-wire
cable amplifier interface. The Tx gain control select bit in
Register 0x0F changes the interpretation of the bits in Registers
0x13, 0x17, 0x1B, and 0x1F. See the Cable Driver Gain Control
section register description.
Data transfers to the gain programmable cable driver amplifier
are initiated by the following four conditions.
1.
2.
Power-Up and Hardware Reset—Upon initial power-up
and every hardware reset, the AD9879 clears the contents
of the gain control registers to 0, which defines the lowest
gain setting of the AD832x. Thus, the AD9879 writes all 0s
out of the 3-wire cable amplifier control interface.
Software Reset—Writing a 1 to Bit 5 of Address 0x00
initiates a software reset. Upon a software reset, the
AD9879 clears the contents of the gain control registers to
0 for the lowest gain and sets the profile select to 0. The
AD9879 writes all 0s out of the 3-wire cable amplifier
control interface if the gain was previously on a different
setting (other than 0).
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3.
4.
Once a new stable gain value is detected (48 MCLK to
64 MCLK cycles after initiation), a data write starts with
CA_EN going low. The AD9879 always finishes a write
sequence to the cable driver amplifier once it is started. The
logic controlling data transfers to the cable driver amplifier uses
up to 200 MCLK cycles and is designed to prevent erroneous
write cycles from occurring.
Change in Profile Selection—The AD9879 samples the
PROFILE input pin together with the two profile select bits
and writes to the AD832x gain control registers when a
change in profile and gain is determined. The data written
to the cable driver amplifier comes from the AD9879 gain
control register associated with the current profile.
Write to AD9879 Cable Driver Amplifier Control
Registers—The AD9879 writes gain control data associated
with the current profile to the AD832x whenever the
selected AD9879 cable driver amplifier gain setting is
changed.