MAX19708ETM+T Maxim Integrated Products, MAX19708ETM+T Datasheet - Page 7

• Manufacturer Part Number: MAX19708ETM+T
• Description: IC ANLG FRNT END 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19708ETM+T

• Number Of Bits: 10
• Number Of Channels: 4
• Power (watts): 36.9mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
C
CS High to DOUT Active High
AUXILIARY DACs (DAC1, DAC2, DAC3)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Gain Error
Zero-Code Error
Output-Voltage Low
Output-Voltage High
DC Output Impedance
Settling Time
Glitch Impulse
Rx ADC-Tx DAC TIMING CHARACTERISTICS
CLK Rise to Channel-I Output Data
Valid
CLK Fall to Channel-Q Output
Data Valid
I-DAC DATA to CLK Fall Setup
Time
Q-DAC DATA to CLK Rise Setup
Time
CLK Fall to I-DAC Data Hold Time
CLK Rise to Q-DAC Data Hold
Time
CLK Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 7, Note 2)
Falling Edge of CS to Rising Edge
of First SCLK Time
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
SCLK to CS Setup Time
CS High Pulse Width
COM
DD
= 3V, OV
= 0.33µF, unless otherwise noted. C
PARAMETER
DD
= 1.8V, internal reference (1.024V), C
_______________________________________________________________________________________
SYMBOL
t
t
t
t
t
DNL
V
t
10-Bit, 11Msps, Ultra-Low-Power
V
t
t
DOQ
t
DHQ
CSW
L
INL
DSQ
t
t
CSD
GE
CSS
t
t
t
t
ZE
DOI
DHI
DSI
DH
CH
N
DS
CL
CP
CS
OH
OL
< 5pF on all aux-DAC outputs. Typical values are at T
Guaranteed monotonic over codes 100 to
4000 (Note 2)
R
R
R
DC output at midscale
From 1/4 FS to 3/4 FS, within ±10 LSB
From 0 to FS transition
Figure 3 (Note 2)
Figure 3 (Note 2)
Figure 6 (Note 2)
Figure 6 (Note 2)
Figure 6 (Note 2)
Figure 6 (Note 2)
20% to 80%
Bit AD0 set
L
L
L
> 200kΩ
> 200kΩ
> 200kΩ
L
≈ 10pF on all digital outputs, f
CONDITIONS
Analog Front-End
CLK
= 11MHz (50% duty cycle), Rx ADC input
A
MIN
2.56
-1.0
5.3
6.8
10
10
10
10
25
25
50
10
80
= +25°C.) (Note 1)
0
0
0
±1.25
±0.65
±0.7
±0.6
TYP
±15
200
7.0
9.1
2.5
12
24
50
4
1
REFP
MAX
+1.2
11.3
0.1
8.5
= C
UNITS
REFN
%FS
%FS
nV
LSB
LSB
Bits
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
Ω
V
V
•
s
7
=