MAX19708ETM+T Maxim Integrated Products, MAX19708ETM+T Datasheet - Page 17

• Manufacturer Part Number: MAX19708ETM+T
• Description: IC ANLG FRNT END 48-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19708ETM+T

• Number Of Bits: 10
• Number Of Channels: 4
• Power (watts): 36.9mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel I
(CHI) and channel Q (CHQ) are sampled on the rising
edge of the clock signal (CLK) and the resulting data is
Table 1. Rx ADC Output Codes vs. Input Voltage
Figure 2. Rx ADC Transfer Function
11 1111 1110
11 1111 1101
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0011
00 0000 0010
00 0000 0001
00 0000 0000
11 1111 1111
DIFFERENTIAL INPUT
-V
-V
V
V
-V
V
V
REF
REF
REF
REF
VOLTAGE
REF
REF
REF
x 512/512
x 511/512
x 511/512
x 512/512
-512
x 1/512
x 0/512
x 1/512
Rx ADC System Timing Requirements
-511
1 LSB =
-510 -509
______________________________________________________________________________________
2 x V
V
1024
REF
REF
INPUT VOLTAGE (LSB)
-1
(COM)
DIFFERENTIAL INPUT (LSB)
0+ 1
511 (+Full Scale - 1 LSB)
510 (+Full Scale - 2 LSB)
-511 (-Full Scale +1 LSB)
V
REF
10-Bit, 11Msps, Ultra-Low-Power
-512 (-Full Scale)
0 (Bipolar Zero)
V
= V
REF
REFP
+509
+510
- V
+1
-1
REFN
+511
+512
(COM)
multiplexed at the D0–D9 outputs. CHI data is updated
on the rising edge and CHQ data is updated on the
falling edge of the CLK. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for CHI and 5.5 clock cycles for CHQ.
D0–D9 are the Rx ADC digital logic outputs when the
MAX19708 is in receive mode. This bus is shared with
the Tx DAC digital logic inputs and operates in half-
duplex mode. D0–D9 are the Tx DAC digital logic inputs
when the MAX19708 is in transmit mode. The logic level
is set by OV
ing is offset binary (Table 1). Keep the capacitive load
on the digital outputs D0–D9 as low as possible
(< 15pF) to avoid large digital currents feeding back into
the analog portion of the MAX19708 and degrading its
dynamic performance. Buffers on the digital outputs iso-
late the outputs from heavy capacitive loads. Adding
100Ω resistors in series with the digital outputs close to
the MAX19708 will help improve ADC performance.
Refer to the MAX19708EVKIT schematic for an example
of the digital outputs driving a digital buffer through
100Ω series resistors.
During SHDN, IDLE, and STBY states, D0–D9 are inter-
nally pulled up to prevent floating digital inputs. To
ensure no current flows through D0–D9 I/O, the external
bus needs to be either tri-stated or pulled up to OV
and should not be pulled to ground.
OFFSET BINARY (D0–D9)
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
DD
Analog Front-End
from 1.8V to V
Digital Input/Output Data (D0–D9)
DD
OUTPUT DECIMAL CODE
. The digital output cod-
1023
1022
513
512
511
1
0
DD
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