MAX19710ETN+T Maxim Integrated Products, MAX19710ETN+T Datasheet - Page 3

IC ANLG FRNT END 56-TQFN

MAX19710ETN+T

Manufacturer Part Number
MAX19710ETN+T
Description
IC ANLG FRNT END 56-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX19710ETN+T

Number Of Bits
10
Number Of Channels
2
Power (watts)
30mW
Voltage - Supply, Analog
3V
Voltage - Supply, Digital
3V
Package / Case
56-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ELECTRICAL CHARACTERISTICS (continued)
(V
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
C
T
A
V
OV
Rx ADC DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
DC Gain Matching
Offset Matching
REFP
DD
DD
= +25°C.) (Note 1)
DD
= 3V, OV
Supply Current
= C
Supply Current
REFN
PARAMETER
DD
= C
= 1.8V, internal reference (1.024V), C
COM
_______________________________________________________________________________________
= 0.33µF, C
L
< 5pF on all aux-DAC outputs, T
SYMBOL
DNL
INL
N
SPI3-Rx mode: f
1.875MHz on both channels; Tx DAC ON
(Tx DAC outputs at midscale); aux-DACs
ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OV
aux-DACs ON and at midscale,
aux-ADC ON
Idle mode: f
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV
aux-ADC OFF
FD mode: f
on both DAC channels; f
both ADC channels; aux-DACs ON and at
midscale, aux-ADC ON
SPI1-Rx and SPI3-Rx modes: f
7.5MHz, f
channels; DAC input bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
SPI2-Tx and SPI4-Tx modes: f
7.5MHz, f
channels; ADC output bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OV
DACs ON and at midscale, aux-ADC ON
Idle mode: f
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV
aux-ADC OFF
N o m i ssi ng cod es over tem p er atur e ( N ote 2)
Residual DC offset error
Includes reference error
L
10-Bit, 7.5Msps, Full-Duplex
≈ 10pF on all digital outputs, f
IN
OUT
CLK
CLK
CLK
= 1.875MHz on both ADC
= 620kHz on both DAC
CONDITIONS
= 7.5MHz, f
CLK
= 7.5MHz; aux-DACs ON
= 7.5MHz; aux-DACs ON
A
= 7.5MHz, f
= T
MIN
IN
= 1.875MHz on
OUT
to T
CLK
CLK
DD
DD
= 620kHz
MAX
IN
DD
DD
;
; aux-
Analog Front-End
=
=
=
, or
, or
CLK
, unless otherwise noted. Typical values are at
= 7.5MHz (50% duty cycle), Rx ADC input
-0.15
-0.8
MIN
10
-5
-5
±0.04
±0.5
±0.4
±0.2
±0.9
TYP
0.94
0.90
12.8
±11
9.5
2.7
4.6
0.5
0.1
0.1
52
+0.15
MAX
+1.0
3.5
+5
+5
12
6
5
UNITS
%FS
%FS
LSB
LSB
LSB
Bits
mA
mA
µA
µA
dB
3

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