ISL98002CRZ-170 Intersil, ISL98002CRZ-170 Datasheet - Page 9

• Manufacturer Part Number: ISL98002CRZ-170
• Description: IC VID DIGITIZER 3CHN AFE 72-QFN
• Manufacturer: Intersil

Specifications of ISL98002CRZ-170

• Number Of Bits: 8
• Number Of Channels: 3
• Power (watts): 535mW
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Package / Case: 72-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
CLOCKINV
HSYNC
VSYNC
HSYNC
G7 thru G0
V
VSYNC
R7 thru R0
B7 thru B0
DATACLK
DATACLK
SYMBOL
XTAL
SOG
SOG
COREADC
SADDR
RESET
XTAL
HS
V
V
GND
R
G
B
R
G
B
SDA
V
SCL
CORE
NC
V
V
V
ADC
IN
IN
PLL
IN
IN
IN
IN
OUT
A
D
X
OUT
IN
IN
1
1
2
2
1
2
IN
OUT
OUT
IN
IN
1
2
1
1
IN
2, 20, 33, 53, 55 Reserved. Do not connect anything to these pins.
3, 6, 10, 12, 19
35, 44, 45, 56,
QFN PIN #(s)
46 thru 52, 54
PAD, 23, 34
59 thru 66
36 thru 43
58, 69
1, 5, 9
32, 57
11
18
27
13
14
16
15
25
28
22
24
29
31
30
67
68
70
71
72
21
17
26
4
7
8
9
Analog input. Red channel. DC couple or AC couple through 0.1µF.
Analog input. Green channel. DC couple or AC couple through 0.1µF.
Analog input. Blue channel. DC couple or AC couple through 0.1µF.
Analog input. Sync on Green. Connect to G
Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND. Connect to HSYNC signal through a
680Ω series resistor.
Digital input, 5V tolerant, 500mV hysteresis. Connect to VSYNC signal.
Analog input. Red channel. DC couple or AC couple through 0.1µF.
Analog input. Green channel. DC couple or AC couple through 0.1µF.
Analog input. Blue channel. DC couple or AC couple through 0.1µF.
Analog input. Sync on Green. Connect to G
Digital input, 5V tolerant. When high, inverts the pixel sampling phase by 180°. Tie to GND if unused.
Digital input, 5V tolerant, active low, 70kΩ pull-up to V
the ISL98002. This pin is not necessary for normal use and may be tied directly to the V
Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical
Specifications” table on page 5 for recommended loading). Typical oscillation amplitude is 1.0V
around 0.5V.
Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical
Specifications” table on page 5 for recommended loading). Typical oscillation amplitude is 1.0V
around 0.5V.
Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
3.3V digital output. Red channel, primary pixel data. 56k pull-down when three-stated.
3.3V digital output. Green channel, primary pixel data. 56k pull-down when three-stated.
3.3V digital output. Blue channel, primary pixel data. 56k pull-down when three-stated.
3.3V digital output. Data clock output. Equal to pixel clock rate.
3.3V digital output. Inverse of DATACLK.
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals).
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC
period. This output will pass composite sync signals and Macrovision signals if present on HSYNC
SOG
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND
Ground return.
Internal power for the ADC’s analog. Connect to a 1.8V supply and bypass to GND with 0.1µF.
Internal power for the ADC’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1µF.
Internal power for core logic. Connect to a 1.8V supply and bypass each pin to GND with 0.1µF.
Internal power for the PLL’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1µF.
IN
.
ISL98002
IN
IN
DESCRIPTION
through a 0.01µF capacitor in series with a 500Ω resistor.
through a 0.01µF capacitor in series with a 500Ω resistor.
D
. Take low for at least 1µs and then high again to reset
X
with 0.1µF.
D
D
with 0.1µF.
supply.
A
with 0.1µF.
P-P
P-P
March 26, 2008
centered
centered
IN
FN6535.0
or