ISL98002CRZ-170 Intersil, ISL98002CRZ-170 Datasheet
ISL98002CRZ-170
Specifications of ISL98002CRZ-170
Related parts for ISL98002CRZ-170
ISL98002CRZ-170 Summary of contents
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... All other trademarks mentioned are the property of their respective owners. ISL98002 FN6535.0 to 1.4V video input range P-P ABLC™ 8 RGB/YUV OUT X3 HSYNC OUT VSYNC OUT HS OUT PIXELCLK OUT | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved ...
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... MARKING ISL98002CRZ-140 ISL98002CRZ -140 ISL98002CRZ-170 ISL98002CRZ -170 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. ...
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... ISL98002 Thermal Information Thermal Resistance QFN Package (Note 1 Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp A Recommended Operating Conditions Temperature (Commercial 0°C to +70°C Supply Voltage 3.3V ±10%, 1.8V ±10 ...
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Electrical Specifications Specifications apply for V ISL98002-140, 170MHz for ISL98002-170, f SYMBOL PARAMETER INPUT CHARACTERISTICS (HSYNC ) Input Threshold Voltage IH IL Hysteresis R Input Impedance IN C Input Capacitance IN DIGITAL INPUT CHARACTERISTICS (SDA, SADDR, CLOCKINV ...
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Electrical Specifications Specifications apply for V ISL98002-140, 170MHz for ISL98002-170, f SYMBOL PARAMETER P Total Power Dissipation D ISL98002-140 ISL98002-170 Standby Mode AC TIMING CHARACTERISTICS PLL Jitter Sampling Phase Steps Sampling Phase Tempco Sampling Phase Differential Nonlinearity HSYNC Frequency Range ...
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F SCL t SU:STA t HD:STA SDA IN SDA OUT DATACLK DATACLK Pixel Data FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING HSYNC IN Analog P P Video DATACLK [7: ...
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The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. HSYNC IN The sampling phase setting determines its relative position to the rest of the AFE’s output signals Analog P P Video DATACLK G ...
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Pinout V 1 ADC ADC SOG ADC ...
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Pin Descriptions SYMBOL QFN PIN #( Analog input. Red channel. DC couple or AC couple through 0.1µ Analog input. Green channel. DC couple or AC couple through 0.1µ Analog ...
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Register Listing ADDRESS REGISTER (DEFAULT VALUE) 0x00 Device ID (read only) 0x01 SYNC Status (read only) 0x02 SYNC Polarity (read only) 0x03 HSYNC Slicer (0x33) 0x04 SOG Slicer (0x16) 10 ISL98002 BIT(S) FUNCTION NAME 3:0 Device Revision 1 = initial ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x05 Input configuration (0x00) 0x06 Red Gain (0x55) 0x07 Green Gain (0x55) 0x08 Blue Gain (0x55) 11 ISL98002 BIT(S) FUNCTION NAME 0 Reserved Set Input Coupling 0: AC coupled (positive ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x09 Red Offset (0x80) 0x0A Green Offset (0x80) 0x0B Blue Offset (0x80) 0x0C Offset DAC Configuration (0x00) 0x0D AFE Bandwidth (0x2E) 0x0E PLL Htotal MSB (0x03) 0x0F PLL Htotal LSB (0x20) 0x10 PLL ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x13 PLL Misc (0x04) 0x14 DC Restore and ABLC™ starting pixel MSB (0x00) 0x15 DC Restore and ABLC™ starting pixel LSB (0x03) 0x16 DC Restore Clamp Width (0x10) 0x17 ABLC™ Configuration (0x40) 13 ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x18 Output Format (0x00) 0x19 HS Width (0x10) OUT 0x1A Output Signal Disable (0x00) 0x1B Power Control (0x00) 0x1C PLL Tuning (0x49) 14 ISL98002 BIT(S) FUNCTION NAME 0 Reserved Set ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x1D Red ABLC Target (0x00) 0x1E Green ABLC Target (0x00) 0x1F Blue ABLC Target (0x00) 0x23 DC Restore Clamp (0x18) 15 ISL98002 BIT(S) FUNCTION NAME 7:0 Reserved This is a 2's complement number ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x25 Sync Separator Control (0x00) Technical Highlights The ISL98002 provides all the features of traditional triple channel video AFEs, but adds several next-generation enhancements, bringing performance and ease of use to new levels. ...
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In addition to drift, many AFEs exhibit interaction between the offset and gain controls. When the gain is changed, the magnitude of the offset is changed ...
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TABLE 3. YUV MAPPING (4:2:2) ISL98002 ISL98002 INPUT INPUT OUTPUT SIGNAL CHANNEL ASSIGNMENT Y Green Green Pb Blue Blue Pr Red Red Input Coupling Inputs can be either AC-coupled (default) or DC-coupled (see register 0x05[1]). AC coupling is usually preferred ...
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SOG For component YPbPr signals, the sync signal is embedded on the Y-Channel’s video, which is connected to the green input, hence the name SOG (Sync on Green). The horizontal sync information is encoded onto the video input by adding ...
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... PLLs never settle to the correct value before the next headswitch, rendering the image completely unintelligible. Intersil’s DPLL has the capability to correct large phase changes almost instantly by maximizing the phase error gain while keeping the frequency gain relatively low. This is done by changing the contents of register 0x1C to 0x4C ...
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Macrovision signals from corrupting the black data and potentially adding a small error in the ABLC™ accumulator. After the trailing edge of HSYNC, the start of ABLC™ is delayed by the number ...
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If there is video on Green (or Y-Channel) with no valid SOG signal, the SOG activity detect bit may sometimes report false positives (it will detect SOG when no SOG is actually present). This is due to the presence of ...
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... If the databus is heavily loaded (long traces, many other part on the same bus), this value may need to be reduced. If the databus is lightly loaded, it may be increased. Intersil’s recommendations to minimize EMI are: • Minimize the databus trace length • Minimize the databus capacitive loading. ...
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Reducing Power Dissipation It is possible to reduce the total power consumption of the ISL98002 in applications where power is a concern. There are several techniques that can be used to reduce power consumption: • Buffering Digital Outputs. Switching data ...
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SCL SDA START FIGURE 7. VALID START AND STOP CONDITIONS SCL FROM HOST 1 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER SCL SDA DATA STABLE FIGURE 9. VALID DATA CHANGES ON THE ...
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START Command ISL98002 Serial Bus (Repeat if desired) STOP Command S T Serial Bus Register A Signals from Address Address R the Host T 1 ...
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START Command ISL98002 Serial Bus START Command ISL98002 Serial Bus (Repeat if desired) STOP Command S T Serial Bus Register ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...