AD73360LAR-REEL Analog Devices Inc, AD73360LAR-REEL Datasheet - Page 26

IC ANALOG FRONT END 6CH 28-SOIC

AD73360LAR-REEL

Manufacturer Part Number
AD73360LAR-REEL
Description
IC ANALOG FRONT END 6CH 28-SOIC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD73360LAR-REEL

Number Of Channels
6
Rohs Status
RoHS non-compliant
Number Of Bits
16
Power (watts)
80mW
Voltage - Supply, Analog
3V
Voltage - Supply, Digital
3V
Package / Case
28-SOIC (7.5mm Width)
Analog Front End Type
General Purpose
Analog Front End Category
General Purpose
Interface Type
Serial (6-Wire)
Sample Rate
64KSPS
Input Voltage Range
0.789V
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Resolution
16b
Number Of Adc's
6
Power Supply Type
Analog/Digital
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
SOIC W
For Use With
EVAL-AD73360LEB - BOARD EVAL FOR AD73360L
Lead Free Status / RoHS Status
Not Compliant
AD73360L
Programming a Single AD73360L for Mixed Mode Operation
This section describes a typical sequence in programming a
single AD73360L to operate in Mixed Mode. The device is
configured in Nonframe Sync Loop-Back (see Figure 11), which
allows the DSP’s Tx Register to determine how many words are
sent to the device during one sample interval. In Nonframe
Sync Loop-Back mode, care must be taken when writing to
the AD73360L that an ADC result or register read result con-
tained in the device’s serial register is not corrupted by a write.
The best way to avoid this is to only write control words when
the AD73360L has no more data to send. This can limit the
number of times a DSP can write to the AD73360L and is
dependant on the SCLK speed and the number of channels
powered up. In this example it is assumed that there are only
two channels powered up and that there is adequate time to
transmit data after the ADC results have been read.
*ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS.
POWER-UP CHANNEL 1 AND 2 AND SET GAINS
SET MIXED MODE
SET 8kHz SAMPLING
POWER-UP REFERENCE
RECEIVE VALID ADC DATA
RECEIVE VALID ADC DATA
CHANGE GAIN ON CHANNEL 1
STEP 1
STEP 2
STEP 3
STEP 4
STEP 5
STEP 6
STEP 7
1000 0001 0000 0011
1000 0011 1111 1010
1000 0010 1110 0000
1000 0000 0000 0010
0111 1111 1111 1111
0111 1111 1111 1111
1000 0011 1000 0010
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
CONTROL WORD
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
DSP Tx REG
APPENDIX B
0000 0000 0000 0000
1011 1001 0000 0011
1011 1011 1111 1010
1011 1010 1110 0000
1000 0000 0000 0000
1111 0000 0000 0000
xxxx xxxx xxxx xxxx
INVALID DATA
ADC WORD 1*
ADC WORD 1*
ADC WORD 1*
ADC WORD 1*
ADC WORD 1
ADC WORD 2
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
DEVICE 1
In Step 1, the device has just been reset and the on first output
event the AD73360L presents an invalid ADC sample word .
Once this word has been received the DSP can begin transmit-
ting programming information to the AD73360L. The first
control word sets the sampling rate at 8 kHz. In Step 2, the
DSP instructs the AD73360L to power up channels 1 and 2
and sets the gain of each. No data is read from the AD73360L
at this point. Steps 3 and 4 set the reference and places the part
into Mixed Mode. In Steps 5 and 6 valid ADC results are read
from the AD73360L and in Step 7 the DSP sends an instruc-
tion to the AD73360L to change the gain of Channel 1.
This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled.
It is important to ensure there is no latency (separation) between control words in
a cascade configuration. This is especially the case when programming Control
Register B, as it contains settings for SCLK and DMCLK rates.
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0000
1111 0000 0000 0000
1111 0000 0000 0000
ADC WORD 1
ADC WORD 2
ADC WORD 2
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG
DSP Rx REG

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