AD73360LAR-REEL Analog Devices Inc, AD73360LAR-REEL Datasheet - Page 21

• Manufacturer Part Number: AD73360LAR-REEL
• Description: IC ANALOG FRONT END 6CH 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73360LAR-REEL

• Number Of Channels: 6
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Power (watts): 80mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 28-SOIC (7.5mm Width)
• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Serial (6-Wire)
• Sample Rate: 64KSPS
• Input Voltage Range: 0.789V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 16b
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC W
• For Use With: EVAL-AD73360LEB - BOARD EVAL FOR AD73360L
• Lead Free Status / RoHS Status: Not Compliant

PERFORMANCE
As the AD73360L is designed to provide high-performance,
low-cost conversion, it is important to understand the means by
which this high performance can be achieved in a typical appli-
cation. This section will, by means of spectral graphs, outline
the typical performance of the device and highlight some of the
options available to users in achieving their desired sample rate,
either directly in the device or by doing some post-processing in
the DSP, while also showing the advantages and disadvantages
of the different approaches.
Encoder Section
The encoder section samples at DMCLK/256, which gives a
64 kHz output rate for DMCLK equal to 16.384 MHz. The
noise-shaping of the sigma-delta modulator also depends on the
frequency at which it is clocked, which means that the best
dynamic performance in a particular bandwidth is achieved by
oversampling at the highest possible rate. If we assume that the
signals of interest are in the bandwidth of dc–4 kHz, then sam-
pling at 64 kHz gives a spectral response which ensures good
SNR performance in that bandwidth, as shown in Figure 20.
DSP CONTROL
TO RESET
DSP CONTROL
TO SE
–100
–120
–140
MCLK
MCLK
–20
–40
–60
–80
0
0
8
CLK
CLK
D
D
RESET
74HC74
74HC74
1/2
1/2
FREQUENCY – kHz
Q
Q
16
SE SIGNAL SYNCHRONIZED
TO MCLK
RESET SIGNAL SYNCHRONIZED
TO MCLK
SNR = 59.0dB (DC TO f
SNR = 78.2dB (DC TO 4kHz)
24
S
/2)
32
The sampling rate can be varied by programming the Decimation
Rate Divider settings in CRB. For a DMCLK of 16.384 MHz
sample rates of 64 kHz, 32 kHz, 16 kHz and 8 kHz are available.
Figure 21 shows the final spectral response of a signal sampled
at 8 kHz using the maximum oversampling rate.
It is possible to generate lower sample rates through reducing
the oversampling ratio by programming the DMCLK Rate
Divider Settings in CRB (MCD2-MCD1). This will have the
effect of spreading the quantization noise over a lesser band-
width resulting in a degradation of dynamic performance.
Figure 22 shows a FFT plot of a signal sampled at 8 kHz rate
produced by reducing the DMCLK Rate.
–100
–120
–140
–100
–120
–140
–20
–40
–60
–80
–20
–40
–60
–80
0
0
0
0
FREQUENCY – kHz
FREQUENCY – kHz
2
2
SNR = 72.2dB (DC TO f
SNR = 78dB (DC TO 4kHz)
AD73360L
S
/2)
4
4