MAX19713ETN+ Maxim Integrated Products, MAX19713ETN+ Datasheet - Page 28

• Manufacturer Part Number: MAX19713ETN+
• Description: IC ANLG FRONT END 45MSPS 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19713ETN+

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 91.8mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The fastest method to perform sequential conversions
with the aux-ADC is by sending consecutive commands
setting AD10 = 1, AD0 = 1. With this sequence the
CS/WAKE falling edge shifts data from the previous con-
version on to DOUT and the rising edge of CS/WAKE
10-Bit, 45Msps, Full-Duplex
Analog Front-End
28
Figure 8. Aux-ADC Conversions Timing
CS/WAKE
CS/WAKE
DOUT
DOUT
SCLK
SCLK
DIN
DIN
______________________________________________________________________________________
1. SINGLE AUX-ADC CONVERSION WITH CONVERSION DATA READOUT AT A LATER TIME
2. CONTINUOUS AUX-ADC CONVERSIONS
AUX-ADC REGISTER
ADDRESS
AUX-ADC REGISTER
ADDRESS
AD10 = 0, AD0 = 1,
PERFORM CONVERSION,
DOUT DISABLED
DOUT TRANSITIONS FROM
HIGH IMPEDANCE TO LOGIC-
HIGH INDICATING START OF
CONVERSION
DOUT TRANSITIONS LOW
INDICATING END OF CONVERSION,
DATA IS AVAILABLE AND CAN BE
SHIFTED OUT IF DOUT IS ENABLED,
AD0 CLEARED
AD10 = 1, AD0 = 1,
PERFORM CONVERSION,
DOUT ENABLED
DOUT TRANSITIONS FROM
HIGH IMPEDANCE TO LOGIC-
HIGH INDICATING START OF
FIRST CONVERSION
DOUT TRANSITIONS LOW
INDICATING END OF FIRST
CONVERSION, DATA IS AVAILABLE
AND CAN BE SHIFTED OUT IF DOUT
IS ENABLED, AD0 CLEARED
1
0
0
1
0
0
1
1
0
0
1
1
t
CSD
1
1
16
16
1
1
t
CONV
t
DCS
1
IF AUX-ADC CONVERSION
DOES NOT NEED TO BE
READ IMMEDIATELY, THE SPI
INTERFACE IS FREE AND
CAN BE USED FOR OTHER
FUNCTIONS, SUCH AS
HOUSEKEEPING AUX-DAC
ADJUSTMENT, ETC.
AD10 = 1, AD0 = 0,
AUX-ADC IDLE
(NO CONVERSION),
DOUT ENABLED AND
CONVERSION DATA IS
SHIFTED OUT ON NEXT
CS/WAKE FALLING EDGE
AD10 = 1, AD0 = 1,
PERFORM CONVERSION,
DOUT ENABLED
FIRST 10-BIT AUX-ADC
CONVERSION RESULT IS
SHIFTED OUT ON DOUT ON
THE FALLING EDGE OF SCLK
MSB FIRST
DOUT TRANSITIONS HIGH
INDICATING START OF
SECOND CONVERSION
DOUT TRANSITIONS LOW
INDICATING END OF SECOND
CONVERSION, DATA IS AVAILABLE
AND CAN BE SHIFTED OUT IF DOUT
IS ENABLED, AD0 CLEARED
1
0
D9
1
10
D1
16
11
D0
12
1
13
0
1
0
D0 HELD
14
1
1
loads the next conversion command at DIN. Allow
enough time for each conversion to complete before
sending the next conversion command. See Figure 8 for
single and continuous conversion examples.
15
1
16
1
AUX-ADC REGISTER
ADDRESS
FIRST FALLING EDGE OF
CS/WAKE AFTER DOUT IS
ENABLED STARTS SHIFTING THE
AUX-ADC CONVERSION DATA ON
THE FALLING EDGE OF SCLK
10-BIT AUX-ADC
CONVERSION RESULT IS
SHIFTED OUT ON DOUT ON
THE FALLING EDGE OF SCLK
MSB FIRST
0
0
1
AD10 = 1, AD0 = 1,
PERFORM CONVERSION,
DOUT ENABLED
SECOND 10-BIT AUX-ADC
CONVERSION RESULT IS
SHIFTED OUT ON DOUT ON
THE FALLING EDGE OF SCLK
MSB FIRST
DOUT TRANSITIONS HIGH
INDICATING START OF
THIRD CONVERSION
DOUT TRANSITIONS LOW
INDICATING END OF THIRD
CONVERSION, DATA IS AVAILABLE
AND CAN BE SHIFTED OUT IF DOUT
IS ENABLED, AD0 CLEARED
1
1
0
16
D9
1
1
10
D1
1
D0
11
DIN SET HIGH DURING SINGLE READ
D9
12
1
t
CD
13
0
10
D1
D0 HELD
14
1
11
D0
CONVERSION RESULT DATA
BIT D0 IS HELD FOR THE SIX
LEAST SIGNIFICANT BITS
DOUT TRANSITIONS TO
HIGH IMPEDANCE
15
1
16
1
D0 HELD
t
CHZ
16