ISL12020MIRZ Intersil, ISL12020MIRZ Datasheet - Page 21

• Manufacturer Part Number: ISL12020MIRZ
• Description: IC RTC/CALENDAR TEMP SNSR 20-DFN
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12020MIRZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Final Digital Trimming Register (FDTR)
This register shows the final setting of DT after
temperature correction. It is read-only; the user cannot
overwrite a value to this register. The value is accessible
as a means of monitoring the temperature compensation
function. The corresponding clock adjustment values are
shown in Table 19. The FDTR setting has both positive
and negative settings to adjust for any offset in the
crystal.
.
ALARM Registers (10h to 15h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte
functions as an enable bit (enable = “1”). These enable
bits specify which alarm registers (seconds, minutes,
etc.) are used to make the comparison. Note that there
is no alarm byte for year.
TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL
ADDR
ADDR
0Eh
0Fh
TABLE 18. FINAL DIGITAL TRIMMING REGISTER
TABLE 17. FINAL ANALOG TRIMMING REGISTER
FDTR<2:0>
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
7
0
7
0
DIGITAL TRIMMING REGISTER
6
0
6
0
FATR5 FATR4 FATR3 FATR2 FATR1 FATR0
5
0
5
FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
4
DECIMAL
21
4
-10
10
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
1
2
3
4
5
6
7
8
9
0
3
3
2
2
ADJUSTMENT
-152.5
-213.5
-274.5
152.5
213.5
274.5
-30.5
-91.5
1
ppm
30.5
91.5
-122
-183
-244
-305
122
183
244
305
1
-61
61
0
0
ISL12020M
0
0
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match
occurs between the alarm registers and the RTC
registers. Any one alarm register, multiple registers, or
all registers can be enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
• Single Event Mode is enabled by setting the bit 7
• Interrupt Mode is enabled by setting the bit 7 on
To clear a single event alarm, the ALM bit in the status
register must be set to “0” with a write. Note that if the
ARST bit is set to 1 (address 08h, bit 7), the ALM bit will
automatically be cleared when the status register is read.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = “0”)
• A single alarm will occur on January 1 at 11:30 a.m.
• Set Alarm registers as follows:
REGISTER
on any of the Alarm registers (ESCA0... EDWA0) to
“1”, the IM bit to “0”, and disabling the frequency
output. This mode permits a one-time match
between the Alarm registers and the RTC registers.
Once this match occurs, the ALM bit is set to “1” and
the IRQ/F
remain low until the ALM bit is reset. This can be
done manually or by using the auto-reset feature.
any of the Alarm registers (ESCA0... EDWA0) to “1”,
the IM bit to “1”, and disabling the frequency output.
The IRQ/F
an alarm occurs. This means that once the interrupt
mode alarm is set, it will continue to alarm for each
occurring match of the alarm and present time. This
mode is convenient for hourly or daily hardware
interrupts in microcontroller applications such as
security cameras or utility meter reading.
ALARM
DWA0
MNA0
MOA0
SCA0
HRA0
DTA0
OUT
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
OUT
output will be pulled low and will
output will now be pulsed each time
BIT
00h Seconds
B0h Minutes set to
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
disabled
30, enabled
enabled
enabled
enabled
disabled
DESCRIPTION
February 11, 2010
FN6667.4