ISL1208IRT8Z-TK Intersil, ISL1208IRT8Z-TK Datasheet - Page 19

• Manufacturer Part Number: ISL1208IRT8Z-TK
• Description: IC RTC/CALENDER I2C 8-TDFN
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL1208IRT8Z-TK

• Memory Size: 2B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A system to implement temperature compensation would
consist of the ISL1208, a temperature sensor, and a
microcontroller. These devices may already be in the system
so the function will just be a matter of implementing software
and performing some calculations. Fairly accurate
temperature compensation can be implemented just by
using the crystal manufacturer’s specifications for the
turnover temperature T
formula for calculating the oscillator adjustment necessary is
Equation 3:
Once the temperature curve for a crystal is established, then
the designer should decide at what discrete temperatures
the compensation will change. Since drift is higher at
extreme temperatures, the compensation may not be
needed until the temperature is greater than +20°C from T
A sample curve of the ATR setting vs Frequency Adjustment
for the ISL1208 and a typical RTC crystal is given in
Figure 18. This curve may vary with different crystals, so it is
good practice to evaluate a given crystal in an ISL1208
circuit before establishing the adjustment values.
This curve is then used to figure what ATR and DTR settings
are used for compensation. The results would be placed in a
lookup table for the microcontroller to access.
Note that the ATR register affects the F
directly. Also, the DTR setting will affect the F
for all but the 32.768Khz setting, due to the clock correction
in the divider chain.
Layout Considerations
The crystal input at X1 has a very high impedance, and
oscillator circuits operating at low frequencies such as
32.768kHz are known to pick up noise very easily if layout
precautions are not followed. Most instances of erratic
clocking or large accuracy errors can be traced to the
susceptibility of the oscillator circuit to interference from
adjacent high speed clock or data lines. Careful layout of the
Adjustment(ppm)
FIGURE 18. ATR SETTING vs OSCILLATOR FREQUENCY
-10
-20
-30
-40
90
80
70
60
50
40
30
20
10
0
0
ADJUSTMENT
5
=
10 15 20 25 30 35 40 45 50 55 60
(
T T
–
0
and the drift coefficient (β). The
0
) 2
∗ β
ATR SETTING
19
OUT
frequency
OUT
frequency
(EQ. 3)
0
ISL1208
.
RTC circuit will avoid noise pickup and insure accurate
clocking.
Figure 19 shows a suggested layout for the ISL1208 device
using a surface mount crystal. Two main precautions should
be followed:
In addition, it is a good idea to avoid a ground plane under
the X1 and X2 pins and the crystal, as this will affect the load
capacitance and therefore the oscillator accuracy of the
circuit. If the IRQ/FOUT pin is used as a clock, it should be
routed away from the RTC device as well. The traces for the
V
be routed around the crystal.
Battery Backup Considerations
The ISL1208 device provides a V
battery backup input. The battery voltage can vary from 1.8V
up to 5.5V, independent of the V
internal switch automatically connects the VBAT supply to
the to the internal power node when V
and switches back to V
Since this battery switch draws power from the battery, it is
very low power and not very fast. If the V
quickly to 0V, there is not enough time for the switch to
connect the V
SRAM contents can be lost or corrupted. It is a good idea to
keep power-down ramps longer than 50us to insure data
retention.
Battery drain can be minimized by using the LPMODE
option. Since normally the V
monitored in order to switch at the lower voltage, two
comparator function are needed during battery backup.
LPMODE shuts off one of the comparators and just
compares V
about 500nA of VBAT current at 3.0V. Do not use LPMODE
when V
device in battery backup mode.
1. Do not run the serial bus lines or any high speed logic
2. Add a ground trace around the crystal with one end
BAT
FIGURE 19. SUGGESTED LAYOUT FOR ISL1208 AND
lines in the vicinity of the crystal. These logic level lines
can induce noise in the oscillator circuit to cause
misclocking.
terminated at the chip ground. This will provide
termination for emitted noise in the vicinity of the RTC
device.
and V
BAT
CC
≥ V
DD
BAT
CRYSTAL
DD
pins can be treated as a ground, and should
to V
source to the internal power node, and the
- 0.2V, to avoid permanently placing the
BAT
DD
to activate switchover. This saves
when power returns.
BAT
DD
and V
BAT
supply voltage. An
pin which is used for a
DD
DD
DD
power goes away,
need to be
drops too
September 12, 2008
FN8085.8