ISL1208IRT8Z-TK Intersil, ISL1208IRT8Z-TK Datasheet - Page 14

• Manufacturer Part Number: ISL1208IRT8Z-TK
• Description: IC RTC/CALENDER I2C 8-TDFN
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL1208IRT8Z-TK

• Memory Size: 2B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The effective series load capacitance is the combination of
C
For example, C
100000) = 4.5pF, and C
entire range for the series combination of load capacitance
goes from 4.5pF to 20.25pF in 0.25pF steps. Note that these
are typical values.
BATTERY MODE ATR SELECTION (BMATR <1:0>)
Since the accuracy of the crystal oscillator is dependent on
the V
to adjust the capacitance between V
device switches between power sources.
DIGITAL TRIMMING REGISTER (DTR <2:0>)
The digital trimming bits DTR0, DTR1, and DTR2 adjust the
average number of counts per second and average the ppm
error to achieve better accuracy.
• DTR2 is a sign bit. DTR2 = “0” means frequency
• DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm
A range from -60ppm to +60ppm can be represented by
using these three bits (see Table 5).
C
C
X1
LOAD
LOAD
compensation is >0. DTR2 = “1” means frequency
compensation is <0.
adjustment and DTR0 gives 20ppm adjustment.
and C
DD
BMATR1
=
=
/V
0
0
1
1
⎛
⎝
---------------------------------- -
⎛
⎝
BAT
---------- -
C
16 b5
---------------------------------------------------------------------------------------------------------------------------- -
X2
1
X1
⋅
in Equation 2.:
operation, the ISL1208 provides the capability
LOAD
1
+
---------- -
C
+
1
8 b4
X2
⋅
⎞
⎠
(ATR = 00000) = 12.5pF, C
LOAD
+
BMATR0
4 b3
⋅
0
1
0
1
14
(ATR = 011111) = 20.25pF. The
+
2 b2
2
⋅
+
0pF
-0.5pF (≈ +2ppm)
+0.5pF (≈ -2ppm)
+1pF (≈ -4ppm)
DD
1 b1
⋅
and V
(C
CAPACITANCE
BAT
+
0.5 b0
DELTA
BAT
TO C
⋅
LOAD
when the
+
VDD
9
⎞ pF
⎠
(ATR =
(EQ. 2)
)
ISL1208
Alarm Registers
Addresses [0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
• Single Event Mode is enabled by setting the ALME bit to
• Interrupt Mode is enabled by setting the ALME bit to “1”,
To clear an alarm, the ALM bit in the status register must be
set to “0” with a write. Note that if the ARST bit is set to 1
(address 07h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
“1”, the IM bit to “0”, and disabling the frequency output.
This mode permits a one-time match between the alarm
registers and the RTC registers. Once this match occurs,
the ALM bit is set to “1” and the IRQ output will be pulled
low and will remain low until the ALM bit is reset. This can
be done manually or by using the auto-reset feature.
the IM bit to “1”, and disabling the frequency output. The
IRQ output will now be pulsed each time an alarm occurs.
This means that once the interrupt mode alarm is set, it
will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for
hourly or daily hardware interrupts in microcontroller
applications such as security cameras or utility meter
reading.
DTR2
0
0
0
0
1
1
1
1
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR REGISTER
DTR1
0
0
1
1
0
0
1
1
DTR0
0
1
0
1
0
1
0
1
FREQUENCY
ESTIMATED
September 12, 2008
0 (default)
PPM
+20
+40
+60
-20
-40
-60
0
FN8085.8