IDT1339-2DVGI IDT, Integrated Device Technology Inc, IDT1339-2DVGI Datasheet - Page 18

• Manufacturer Part Number: IDT1339-2DVGI
• Description: IC SERIAL RTC I2C LP 8-MSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Calendar/Alarmr

Specifications of IDT1339-2DVGI

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 1339-2DVGI

Timing Diagram
IDT® REAL-TIME CLOCK WITH SERIAL I
IDT1339
REAL-TIME CLOCK WITH SERIAL I
Note 7: Using recommended crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum t
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement t
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
t
Note 12: C
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter t
voltage range of 0.0V <
SU:DAT
= 1000 + 250 = 1250 ns before the SCL line is released.
B
—total capacitance of one bus line in pF.
V
2
HD:DAT
OSF
CC
C INTERFACE
2
<
C INTERFACE
is the period of time the oscillator must be stopped for the OSF flag to be set over the
V
CC
need only be met if the device does not stretch the LOW period (t
MAX and 1.3 V < V
18
BACKUP
< 3.7 V.
IDT1339
SU:DAT
> to 250 ns must
LOW
) of the SCL
REV K 032910
R(MAX)
IHMIN
RTC
+
of