IDT1339-31DCGI8 IDT, Integrated Device Technology Inc, IDT1339-31DCGI8 Datasheet - Page 7
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IDT1339-31DCGI8
Manufacturer Part Number
IDT1339-31DCGI8
Description
IC SERIAL RTC I2C LP 8-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock/Calendar/Alarmr
Datasheet
1.IDT1339-2DCGI8.pdf
(27 pages)
Specifications of IDT1339-31DCGI8
Date Format
YY-MM-DD-dd
Time Format
HH:MM:SS (12/24 hr)
Interface
I²C, 2-Wire Serial
Voltage - Supply
3.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC
Bus Type
Serial (I2C)
Operating Supply Voltage (typ)
3.3V
Package Type
SOIC
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Pin Count
8
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
1339-31DCGI8
Time and Date Operation
The time and date information is obtained by reading the
appropriate register bytes. Table 3 shows the RTC registers.
The time and date are set or initialized by writing the
appropriate register bytes. The contents of the time and
date registers are in the BCD format. The IDT1339 can be
run in either 12-hour or 24-hour mode. Bit 6 of the hours
register is defined as the 12- or 24-hour mode-select bit.
When high, the 12-hour mode is selected. In the 12-hour
mode, bit 5 is the AM/PM bit with logic high being PM. In the
24-hour mode, bit 5 is the second 10-hour bit (20 to 23
hours). All hours values, including the alarms, must be
re-entered whenever the 12/24-hour mode bit is changed.
The century bit (bit 7 of the month register) is toggled when
the years register overflows from 99 to 00. The day-of-week
register increments at midnight. Values that correspond to
the day of week are user-defined, but must be sequential
(i.e., if 1 equals Sunday, then 2 equals Monday and so on).
Illogical time and date entries result in undefined operation.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors when
the internal registers update. When reading the time and
date registers, the user buffers are synchronized to the
internal registers on any start or stop, and when the address
pointer rolls over to zero. The countdown chain is reset
whenever the seconds register is written. Write transfers
occurs on the acknowledge pulse from the device. To avoid
rollover issues, once the countdown chain is reset, the
remaining time and date registers must be written within one
second. If enabled, the 1 Hz square-wave output transitions
high 500 ms after the seconds data transfer, provided the
oscillator is already running.
IDT® REAL-TIME CLOCK WITH SERIAL I
IDT1339
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
2
C INTERFACE
7
Alarms
The IDT1339 contains two time of day/date alarms. Alarm 1
can be set by writing to registers 07h to 0Ah. Alarm 2 can be
set by writing to registers 0Bh to 0Dh. The alarms can be
programmed (by the Alarm Enable and INTCN bits of the
Control Register) to activate the SQW/INT output on an
alarm match condition. Bit 7 of each of the time of day/date
alarm registers are mask bits (Table 4). When all the mask
bits for each alarm are logic 0, an alarm only occurs when
the values in the timekeeping registers 00h to 06h match the
values stored in the time of day/date alarm registers. The
alarms can also be programmed to repeat every second,
minute, hour, day, or date. Table 4 shows the possible
settings. Configurations not listed in the table result in
illogical operation.
The DY/DT bits (bit 6 of the alarm day/date registers) control
whether the alarm value stored in bits 0 to 5 of that register
reflects the day of the week or the date of the month. If
DY/DT is written to a logic 0, the alarm is the result of a
match with date of the month. If DY/DT is written to a logic
1, the alarm is the result of a match with day of the week.
The device checks for an alarm match once per second.
When the RTC register values match alarm register
settings, the corresponding Alarm Flag ‘A1F’ or ‘A2F’ bit is
set to logic 1. If the corresponding Alarm Interrupt Enable
‘A1IE’ or ‘A2IE’ is also set to logic 1 and the INTCN bit is set
to logic 1, the alarm condition activates the SQW/INT signal.
If the BBSQI bit is set to 1, the INT output activates while the
part is being powered by V
remains active until the alarm flag is cleared by the user.
BACKUP
. The alarm output
IDT1339
REV K 032910
RTC