M48T512Y-70PM1 STMicroelectronics, M48T512Y-70PM1 Datasheet - Page 9

• Manufacturer Part Number: M48T512Y-70PM1
• Description: IC TIMEKPR NVRAM 4MBIT 5V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T512Y-70PM1

• Memory Size: 4M (512K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Clock Format: BCD
• Clock Ic Type: Timekeeper
• Memory Configuration: 512K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: DIP
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Nvram Features: RTC, Internal Battery, XTAL
• Access Time: 70ns
• Memory Case Style: DIP
• Bus Type: Parallel
• User Ram: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 32
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2856-5

M48T512Y, M48T512V
2.2
Figure 5.
Figure 6.
A0-A18
E
W
DQ0-DQ7
A0-A18
E
W
DQ0-DQ7
WRITE mode
The M48T512Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are low state after the address inputs are stable.
The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE
is terminated by the earlier rising edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for a minimum of t
t
must be valid t
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on W will disable the outputs t
falls.
WRITE AC waveforms, WRITE enable controlled
WRITE AC waveforms, chip enable controlled
WHAX
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in
DVWH
tAVEL
tAVWL
tAVEL
tAVWL
prior to the end of WRITE and remain valid for t
tWLQZ
Doc ID 5747 Rev 6
tAVEH
tAVWH
tWLWH
VALID
tAVAV
VALID
tAVAV
tELEH
tDVEH
tDVWH
DATA INPUT
DATA INPUT
tWHDX
tEHDX
EHAX
tWHQX
tEHAX
WHDX
tWHAX
from chip enable or
Operating modes
afterward. G
WLQZ
after W
AI02386
AI02387
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