M48T512Y-70PM1 STMicroelectronics, M48T512Y-70PM1 Datasheet - Page 10

• Manufacturer Part Number: M48T512Y-70PM1
• Description: IC TIMEKPR NVRAM 4MBIT 5V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T512Y-70PM1

• Memory Size: 4M (512K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Clock Format: BCD
• Clock Ic Type: Timekeeper
• Memory Configuration: 512K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: DIP
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Nvram Features: RTC, Internal Battery, XTAL
• Access Time: 70ns
• Memory Case Style: DIP
• Bus Type: Parallel
• User Ram: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 32
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2856-5

Operating modes
Table 4.
1. Valid for ambient operating temperature: T
2. C
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
10/23
t
t
WHQX
WLQZ
Symbol
L
t
t
t
t
t
t
t
t
t
t
t
t
t
WLWH
WHAX
DVWH
WHDX
AVWH
EHDX
AVWL
EHAX
DVEH
AVEH
AVEL
ELEH
= 5pF.
AVAV
(2)(3)
(2)(3)
WRITE mode AC characteristics
Data retention mode
With valid V
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting
itself when V
impedance and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the current addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
memory will be in a write protected state, provided the V
M48T512Y/V may respond to transient noise spikes on V
window during the time the device is sampling V
supply lines is recommended. When V
power to the internal battery, preserving data and powering the clock. The internal energy
source will maintain data in the M48T512Y/V for an accumulated period of at least 10 years
at room temperature. As system power rises above V
the power supply is switched to external V
V
V
battery life.
PFD
PFD
WRITE cycle time
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
Chip enable low to chip enable high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to write enable high
Address valid to chip enable high
WRITE enable high to output transition
(min) plus t
(max). Refer to Application Note (AN1012) on the ST website for more information on
CC
CC
applied, the M48T512Y/V operates as a conventional BYTEWIDE™ static
Parameter
falls between V
REC
(min). Normal RAM operation can resume t
A
(1)
= 0 to 70 °C; V
Doc ID 5747 Rev 6
PFD
(max) and V
CC
CC
= 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
drops below V
CC
Min
. Write protection continues until V
70
50
55
10
30
30
10
60
60
0
0
5
5
5
M48T512Y
PFD
CC
-70
.Therefore, decoupling of the power
(min). All outputs become high
SO
Max
, the battery is disconnected, and
25
SO
CC
CC
, the control circuit switches
fall time is not less than t
that cross into the deselect
REC
Min
85
60
65
15
35
35
15
70
70
0
0
5
5
5
M48T512Y, M48T512V
M48T512V
after V
-85
PFD
CC
Max
30
(min), the
exceeds
CC
reaches
F
. The
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns