M48T512Y-70PM1 STMicroelectronics, M48T512Y-70PM1 Datasheet - Page 8

• Manufacturer Part Number: M48T512Y-70PM1
• Description: IC TIMEKPR NVRAM 4MBIT 5V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T512Y-70PM1

• Memory Size: 4M (512K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Clock Format: BCD
• Clock Ic Type: Timekeeper
• Memory Configuration: 512K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: DIP
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Nvram Features: RTC, Internal Battery, XTAL
• Access Time: 70ns
• Memory Case Style: DIP
• Bus Type: Parallel
• User Ram: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 32
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2856-5

M48T512Y, M48T512V
Table 10. Write Mode AC Characteristics
(T
Note: 1. C
Calibrating the Clock. The M48T512Y/V is driv-
en by a quartz controlled oscillator with a nominal
frequency of 32,768Hz. The devices are factory
calibrated at 25°C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million)
oscillator frequency error at 25°C, which equates
to about ±1.53 minutes per month. When the Cal-
ibration circuit is properly employed, accuracy im-
proves to better than +4 ppm at 25°C. The
oscillation rate of crystals changes with tempera-
ture. The M48T512Y/V design employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 10.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
8/14
A
t
t
WHQX
WLQZ
= 0 to 70 °C)
Symbol
t
t
t
t
t
t
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
t
t
t
t
t
AVE1H
t
t
WLWH
WHAX
WHDX
DVWH
AVWH
AVWL
EHAX
EHDX
ELEH
DVEH
AVAV
AVEL
(1, 2)
L
(1, 2)
= 5pF.
Write Cycle Time
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
Write Enable High to Input Transition
Chip Enable High to Input Transition
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
Parameter
tracting counts slows the clock down. The Calibra-
tion bits occupy the five lower order bits (D4-D0) in
the Control Register 7FFF8h. These bits can be
set to represent any value between 0 and 31 in bi-
nary form. Bit D5 is a Sign bit; '1' indicates positive
calibration, '0' indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 actual oscillator cycles; that
is, +4.068 or –2.034 ppm of adjustment per cali-
bration step in the calibration register.
Min
70
50
55
10
30
30
10
60
60
0
0
5
5
5
M48T512Y
-70
Max
25
Min
85
60
65
15
35
35
15
70
70
0
0
5
5
5
M48T512V
-85
Max
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns