M48T512Y-70PM1 STMicroelectronics, M48T512Y-70PM1 Datasheet - Page 3

• Manufacturer Part Number: M48T512Y-70PM1
• Description: IC TIMEKPR NVRAM 4MBIT 5V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T512Y-70PM1

• Memory Size: 4M (512K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Clock Format: BCD
• Clock Ic Type: Timekeeper
• Memory Configuration: 512K X 8
• Supply Voltage Range: 4.5V To 5.5V
• Digital Ic Case Style: DIP
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Rohs Compliant: Yes
• Nvram Features: RTC, Internal Battery, XTAL
• Access Time: 70ns
• Memory Case Style: DIP
• Bus Type: Parallel
• User Ram: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 32
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2856-5

Table 3. Operating Modes
Note: 1. X = V
cess Time (t
nal is stable, providing the E and G access times
are also satisfied. If the E and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access Times (t
Enable Access Time (t
three-state Data I/O signals is controlled by E and
G. If the outputs are activated before t
data lines will be driven to an indeterminate state
until t
while E and G remain active, output data will re-
main valid for Output Data Hold Time (t
will go indeterminate until the next Address Ac-
cess.
WRITE MODE
The M48T512Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a write is referenced from the latter occurring
falling edge of W or E. A write is terminated by the
earlier rising edge of W or E. The addresses must
be held valid throughout the cycle. E or W must re-
turn high for a minimum of t
or t
another read or write cycle. Data-in must be valid
t
t
write cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G a low on W will disable the outputs t
ter W falls.
DVWH
WHDX
Deselect
Write
Read
Read
Deselect
Deselect
WHAX
Mode
2. See Table 7 for details.
AVQV
prior to the end of write and remain valid for
afterward. G should be kept high during
from Write Enable prior to the initiation of
. If the Address Inputs are changed
IH
AVQV
or V
IL
V
) after the last address input sig-
.
SO
4.5V to 5.5V
3.0V to 3.6V
to V
GLQV
V
V
PFD
or
SO
CC
EHAX
). The state of the eight
(2)
(1)
(min)
from Chip Enable
(2)
ELQV
) or Output
AVQV
AXQX
WLQZ
V
V
V
V
E
X
X
IH
IL
IL
IL
, the
) but
af-
V
V
G
X
X
X
X
IH
IL
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Figure 3. AC Testing Load Circuit
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
C L includes JIG capacitance
DEVICE
UNDER
TEST
V
V
V
W
X
X
X
IH
IH
IL
DQ0-DQ7
High Z
High Z
High Z
High Z
D
D
OUT
IN
M48T512Y, M48T512V
C L = 100pF
650
Battery Back-up Mode
CMOS Standby
Standby
Power
Active
Active
Active
0 to 3V
AI01803C
1.5V
5ns
1.75V
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