ISL1219IUZ Intersil, ISL1219IUZ Datasheet - Page 20
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ISL1219IUZ
Manufacturer Part Number
ISL1219IUZ
Description
IC RTC LP BATT BACK SRAM 10MSOP
Manufacturer
Intersil
Type
Clock/Calendar/NVSRAMr
Specifications of ISL1219IUZ
Memory Size
2B
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-MSOP, Micro10™, 10-uMAX, 10-uSOP
Clock Format
HH
Clock Ic Type
RTC
Interface Type
I2C, Serial
Memory Configuration
2 X 8
Supply Voltage Range
2.7V To 5.5V
Digital Ic Case Style
MSOP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ISL1219IUZ
Manufacturer:
Intersil
Quantity:
490
Company:
Part Number:
ISL1219IUZ
Manufacturer:
Intersil
Quantity:
222
Part Number:
ISL1219IUZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Application Section
Event Detection
The event detection feature of the ISL1219 is intended to be
used for recording the time of single events that involve the
opening of an enclosure, door, etc. The normal method of
detection is with normally closed switch function that opens
to initiate the event. This mechanism is ideal for applications
such as set top boxes, utility meters, security alarm and
camera systems or vending machines.
A typical application diagram is shown in Figure 19. A
microcontroller communicates with the ISL1219 through the
I
set up the outputs frequency control.
The ISL1219 is capable of recording individual event
time/dates using the on-chip registers (Event Registers,
addresses 14h to 19h). Single event times are recorded and
can be read using a multiple address read, similar to reading
the RTC registers. The Event Registers record the initial
event time of a series of events, until the EVT bit is reset.
After EVT is reset, the Timestamp Registers retain the
previous event time until the next Event happens, at which
time the current RTC register contents will be placed in the
Event Registers. The Timestamp Registers cannot be
cleared, only a full power down cycle (V
will erase their contents.
For example, the event function is enabled and the EVT bit
in the Status Register is cleared. Then the EVEN pin is
triggered 3 times before the timestamp register is read. Only
the first Event time will be recorded in the Timestamp
Registers, and will be read. Then the EVT bit is cleared in
the Status Register, and two more events happen. The
2
C serial bus, to set up and read time of the day, alarms, or
20
MICRO C.
SCL
SDA
P0
P1
P2
P3
P4
P5
V
CC
CC
5.1k
and V
3.0V
BAT
5.1k+
= 0V)
32.768kHz
ISL1219
FIGURE 19.
* Optional Pull-up resistors, or use internal current
** The Pull-up resistor on the EVDET-output can vary
from 10k up to 10M or more, depending on the
application
Note: Event Detect Switch Normally Closed
Source
1
2
3
4
5
X1
X2
V
V
EVIN
BAT
DD
previous Timestamp contents are replaced by the time of the
next event after the EVT bit reset.
An additional event action available in the ISL1219 is to stop
the real time clock from advancing. If the event register is set
to enable this function (Register 09h, RTCHLT bit 5 set to 1),
then when the EVIN pin is triggered, the clock counters will
stop and hold the time of the event. This is useful for one
time occurrences such as opening a warranted consumer
product enclosure or exceeding a maximum temperature
inside a device. Once the clock is stopped, the clock
registers must be written with an updated time, then they will
begin advancing immediately. If the RTCHLT bit is still set,
then the next event will again stop the clock.
Event Detect Input Details
The EVIN input is a Schmitt trigger logic input. An event is
detected when it is asserted high. The ISL1219 device has
internal configuration settings which add detection flexibility.
There are four configuration bits in register 09h which are for
EVIN sampling. The ESMP1 and ESMP0 bits control
sampling of the event input status. Reducing the sampling
rate will lower the supply current drain, with the tradeoff of
adding a delay in detecting an event. An event that is long in
duration (i.e. opening a door) would obviously be served well
with the lowest frequency sampling rate and lowest supply
current drain.
The EHYS1 and EHYS0 bits control timer circuits to filter out
switch bouncing, noise or intermittent contacts, by effectively
adding time-based hysteresis to the EVIN input. They are
used only in conjunction with the sampling rate, they cannot
be used alone. The most appropriate use for the hysteresis
function is for glitch or noise filtering on the EVIN input
signal.
ISL1219
EVDET
IRQ/F
SDA
V
SCL
CC
10
9
8
7
6
1M**
2M*
July 15, 2010
FN6314.2