MC88915FN70R2 Freescale Semiconductor, MC88915FN70R2 Datasheet - Page 7

• Manufacturer Part Number: MC88915FN70R2
• Description: IC DRIVER CLK PLL 70MHZ 28-PLCC
• Manufacturer: Freescale Semiconductor
• Type: Clock Driver, Fanout Distribution, Multiplexerr

Specifications of MC88915FN70R2

• Pll: Yes
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 3:8
• Differential - Input:output: No/No
• Frequency - Max: 70MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 70MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MC88915FN70R2TR

TIMING SOLUTIONS
BR1333 — Rev 6
6. Calculation of Total Output–to–Skew between multiple
FEEDBACK
parts (Part–to–Part skew)
By combining the t PD specification and the information in
Note 5, the worst case output–to–output skew between
multiple 88915’s connected in parallel can be calculated.
This calculation assumes that all parts have a common
SYNC input clock with equal delay of that input signal to
each part. This skew value is valid at the 88915 output
pins only (equally loaded), it does not include PCB trace
delays due to varying loads.
With a 1M resistor tied to analog V CC as shown in note
4, the t PD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05ns and
–0.5ns.
between two or more parts, the absolute value of the
distribution of that output given in table 2 must be
subtracted and added to the lower and upper t PD spec
limits respectively. For output Q2, [276 – (–44)] = 320ps is
the absolute value of the distribution. Therefore [–1.05ns
FEEDBACK
SYNC to
SYNC to
(ns)
tPD
(ns)
tPD
To calculate the skew of any given output
–0.50
–0.75
–1.00
–1.25
–1.50
Back, Including Process and Voltage Variation @ 25 C
Back, Including Process and Voltage Variation @ 25 C
3.5
3.0
2.5
2.0
0.5
1.5
1.0
t PD versus Frequency Variation for Q/2 Output Fed
t PD versus Frequency Variation for Q/2 Output Fed
2.5
2.5
(With 1M Resistor Tied to Analog V CC )
(With 1M Resistor Tied to Analog GND)
5.0
5.0
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
7.5
7.5
Figure 3a.
Figure 3c.
10.0
10.0
12.5
12.5
15.0
15.0
17.5
17.5
FEEDBACK
FEEDBACK
SYNC to
SYNC to
7
(ns)
tPD
tPD
(ns)
7. Note 4 explains that the t PD specification was measured
–0.5
–1.0
–1.5
–2.0
3.5
3.0
2.5
2.0
0.5
Back, Including Process and Voltage Variation @ 25 C
1.5
1.0
Back, Including Process and Voltage Variation @ 25 C
– 0.32ns] = –1.37ns is the lower t PD limit, and [–0.5ns +
0.32ns] = –0.18ns is the upper limit. Therefore the worst
case skew of output Q2 between any number of parts is
|(–1.37) – (–0.18)| = 1.19ns. Q2 has the worst case skew
distribution of any output, so 1.2ns is the absolute worst
case output–to–output skew between multiple parts.
and is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10MHz. The fixed offset (t PD ) as described
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of
Figure 3 demonstrate this dependence.
The data presented in Figure 3 is from devices
representing process extremes, and the measurements
were also taken at the voltage extremes (V CC = 5.25V
and 4.75V). Therefore the data in Figure 3 is a realistic
representation of the variation of t PD .
t PD versus Frequency Variation for Q4 Output Fed
t PD versus Frequency Variation for Q4 Output Fed
0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5
(With 1M Resistor Tied to Analog GND)
(With 1M Resistor Tied to Analog V CC )
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
5
10
Figure 3b.
Figure 3d.
15
20
25
MC88915
MOTOROLA