TDA7427AD1 STMicroelectronics, TDA7427AD1 Datasheet - Page 6

• Manufacturer Part Number: TDA7427AD1
• Description: IC SYNTHESIZER/IF COUNTER SO-28
• Manufacturer: STMicroelectronics
• Type: PLL Frequency Synthesizerr

Specifications of TDA7427AD1

• Pll: Yes
• Input: Clock, Crystal
• Output: Clock, Crystal
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: No/No
• Frequency - Max: 290MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 4.5 V ~ 11 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Frequency-max: 290MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TDA7427A
GENERAL DESCRIPTION
This circuit contains a frequency synthesiser and
a loop filter for use in FM/AM radio tuning sys-
tems. Only a VCO is required to build a complete
PLL system. For auto search/stop operation an IF
counter system is available.
For FM and SW AM application, the counter
works in a two-stage configuration. The first stage
is a swallow counter with a two modulus (:32/33)
precounter. The second stage is an 11-bit pro-
grammable counter.
For LW and MW application, a 16-bit programma-
ble counter is available.
The circuit receives the scaling factors for the pro-
grammable counters and the values of the refer-
ence frequencies via a I
The reference frequency is generated by an inter-
nal XTAL oscillator followed by the reference di-
vider. The device can operate with XTAL oscilla-
tor between 4 and 13MHz either in master mode
and in slave mode.
The reference and step frequencies are free se-
lectable. (XTAL frequency divided by an integer
value). The outputs signals of the phase detector
are switching the programmable current sources.
The loop filter integrates their currents to a DC
voltage.
Values of the current sources are programmable
by 6 bits also received via the I
Table 1. Address Organization
6/21
PLL CHARGE PUMP
PLL COUNTER
PLL COUNTER
PLL REF COUNTER
PLL REF COUNTER
PLL LOCK DETECT
IFC REF COUNTER
IFC REF COUNTER
IFC CONTROL
IFC CONTROL
OSC ADJUST
PORT EXTENSION
FUNCTION
SUBAD
0AH
0BH
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
2
C bus interface.
LPIN1/2
2
LDENA
IFCM1
IFENA
C bus.
PC15
RC15
BIT 7
IRC7
IFS2
PC7
RC7
-
-
INLOCK
CURRH
IFCM0
RC14
PC14
BIT 6
IRC6
RC6
IFS1
PC6
-
-
-
MSB
DOUT3
IRC13
RC13
BIT 5
PC13
IRC5
IFS0
PC5
RC5
D3
B1
-
-
To minimize the noise induced by the digital part
of the system, a separate power supply supplies
the internal loop filter amplifier. The loop gain can
be set for different conditions by setting the cur-
rent values of the charge/pump generator.
IF COUNTER SYSTEM
Two separate inputs are available for AM and FM
IF signals. The level of integration is adjustable
by six different measuring cycle times.
The tolerance of the accepted count value is ad-
justable, to reach an optimum compromise for
search speed and precision of the evaluation.
For the FM range the center frequency of the
measured count value is adjustable in 32 steps,
to get the possibility of fitting the IF filter toler-
ance. In the AM range an IF frequency of 448 to
479KHz ( 10.684 to 10.715MHz for AM up-con-
version) with 1KHz steps is available.
PLL FREQUENCY SYNTHESIZER
Input Amplifiers
The signals applied on AM and FM inputs are am-
plified to get a logic level in order to drive the fre-
quency dividers.
The typical input impedance for FM and AM in-
puts is 4k .
DOUT4
IRC12
OSC4
BIT 4
PC12
RC12
IRC4
RC4
PC4
CF4
D2
B0
-
DOUT5
IRC11
OSC3
RC11
BIT 3
PC11
IRC3
PC3
RC3
CF3
A3
D1
-
DOUT6
IRC10
OSC2
PC10
RC10
BIT 2
IRC2
EW2
PC2
RC2
CF2
A2
D0
DOUT2
OSC1
BIT 1
IRC1
IRC9
PM1
EW1
PC1
PC9
RC1
RC9
CF1
A1
DOUT1
OSC0
BIT 0
IRC0
IRC8
EW0
LSB
PC0
PC8
RC0
RC8
PM0
CF0
A0