CY28RS480ZXC Cypress Semiconductor Corp, CY28RS480ZXC Datasheet - Page 4

IC CLOCK GENERATOR 56-TSSOP

CY28RS480ZXC

Manufacturer Part Number
CY28RS480ZXC
Description
IC CLOCK GENERATOR 56-TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Clock Generatorr
Datasheet

Specifications of CY28RS480ZXC

Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP II
Frequency-max
200MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output
-
Input
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY28RS480ZXC
Manufacturer:
MAXIM
Quantity:
160
Part Number:
CY28RS480ZXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document #: 38-07638 Rev. *C
Table 3. Byte Read and Byte Write Protocol (continued)
Control Registers
Byte 0:Control Register 0
Byte 1: Control Register 1
18:11
27:20
Bit
Bit
Bit
19
28
29
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Byte Write Protocol
Description
SRCS[T/C]1
SRCS[T/C]0
RESERVED
SRC [T/C]0
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
CPU[T/C]1
CPU[T/C]0
USB_48
Name
Name
REF2
REF1
REF0
PCI0
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRCS[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
REF2 Output Enable
0 = Disable, 1 = Enable
REF1 Output Enable
0 = Disable, 1 = Enable
REF0 Output Enable
0 = Disable, 1 = Enable
PCI0 Output Enable
0 = Disable, 1 = Enable
USB_48MHz Output Enable
0 = Disable, 1 = Enable
RESERVED
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
27:21
37:30
18:11
Bit
19
20
28
29
38
39
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Description
Description
Byte Read Protocol
Description
CY28RS480
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