ADF4212LBCP-REEL7 Analog Devices Inc, ADF4212LBCP-REEL7 Datasheet - Page 7

• Manufacturer Part Number: ADF4212LBCP-REEL7
• Description: IC PLL FREQ SYNTHESIZER 20LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF/IF)r

Specifications of ADF4212LBCP-REEL7

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 3:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 2.4GHz

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Mnemonic
CP
DGND
RF
AGND
FL
REF
DGND
MUXOUT
CLK
DATA
LE
R
AGND
IF
CP
V
SET
P
IN
2
O
IN
RF
IF
IN
RF
IF
RF
IF
12
13
TSSOP
3
4
5
6
7
8
9, 17
10
11
14
15
16
18
19
MUXOUT
DGND
AGND
DGND
Figure 3. TSSOP Pin Configuration
REF
V
CP
RF
Pin No.
FL
DD
V
P
RF
RF
RF
IN
IN
IF
O
1
1
10
LFCSP
1
2
3
4
5
6
7, 15
8
9
10
11
12
13
14
16
17
1
2
3
4
5
6
7
8
9
ADF4212L
(Not to Scale)
TOP VIEW
Description
RF Charge Pump Output. When enabled, this provides ±I
drives the external RF VCO.
Digital Ground Pin for the RF Digital Circuitry.
Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.
Ground Pin for the RF Analog Circuitry.
Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. See Figure 26. This input can be driven from a TTL or CMOS crystal oscillator, or can
be ac-coupled.
Digital Ground Pin for the IF Digital, Interface, and Control Circuitry.
This multiplexer output allows either the IF/RF lock detect, the scaled RF, the scaled IF, or the scaled
reference frequency to be accessed externally.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is
a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, with the latch selected using the control bits.
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R
therefore,
where R
Ground Pin for the IF Analog Circuitry.
Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.
Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an
external VCO.
Power Supply for the IF Charge Pump. This should be greater than or equal to V
V
DD
2 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.
20
19
18
17
16
15
14
13
12
11
I
CP
V
V
CP
DGND
IF
AGND
R
LE
DATA
CLK
DD
P
SET
SET
IN
MAX
2
IF
2
= 2.7 kΩ and I
IF
IF
=
R
13.5
SET
CP MAX
Rev. C | Page 7 of 28
= 5 mA for both the RF and IF charge pumps.
SET
pin is 0.66 V. The relationship between I
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERMAL PERFORMANCE. THE PAD
SHOULD BE GROUNDED AS WELL.
DGND
AGND
CP
CP
RF
Figure 4. LFCSP Pin Configuration
FL
to the external RF loop filter, which in turn
RF
RF
RF
IN
O
1
2
3
4
5
ADF4212L
(Not to Scale)
DD
TOP VIEW
PIN 1
INDICATOR
/2 and an equivalent input
DD
15 DGND
14 IF
13 AGND
12 R
11 LE
2. In systems where
SET
IN
IF
IF
ADF4212L
CP
and R
SET
is,