ADF4212LBCP-REEL7 Analog Devices Inc, ADF4212LBCP-REEL7 Datasheet

IC PLL FREQ SYNTHESIZER 20LFCSP

ADF4212LBCP-REEL7

Manufacturer Part Number
ADF4212LBCP-REEL7
Description
IC PLL FREQ SYNTHESIZER 20LFCSP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF/IF)r
Datasheet

Specifications of ADF4212LBCP-REEL7

Rohs Status
RoHS non-compliant
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
3:1
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-LFCSP
Frequency-max
2.4GHz
FEATURES
I
Bandwidth RF/IF: 2.4 GHz/1.0 GHz
2.7 V to 3.3 V power supply
Separate V
Programmable dual modulus prescaler
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Fastlock mode
Power-down mode
20-lead TSSOP and 20-lead LFCSP packages
APPLICATIONS
Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA,
Base stations for wireless Radio (GSM, PCS, DCS,
Wireless LANS
Cable TV tuners (CATV)
Communications test equipment
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DD
RF and IF: 8/9, 16/17, 32/33, 64/65
WCDMA)
CDMA, WCDMA)
total: 7.5 mA
P
allows extended tuning voltage
REF
DATA
RF
CLK
IF
LE
IN
IN
IN
ADF4212L
OSCILLATOR
REGISTER
22-BIT
DATA
PRESCALER
PRESCALER
DGND
RF
IF
RF
SDOUT
FUNCTIONAL BLOCK DIAGRAM
AGND
RF
V
B-COUNTER
A-COUNTER
B-COUNTER
A-COUNTER
DGND
DD
12-BIT IF
12-BIT RF
6-BIT RF
6-BIT IF
1
R-COUNTER
R-COUNTER
15-BIT RF
15-BIT IF
IF
Figure 1.
V
DD
AGND
2
IF
V
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The ADF4212L is a dual frequency synthesizer that can be used
to implement local oscillators (LO) in the up-conversion and
down-conversion sections of wireless receivers and transmitters.
It can provide the LO for both the RF and IF sections. It consists
of a low noise digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual modulus prescaler (P/P + 1). The
A (6-bit) and B (12-bit) counters, in conjunction with the dual
modulus prescaler (P/P + 1), implement an N divider (N = BP +
A). In addition, the 15-bit reference counter (R counter) allows
selectable REF
locked loop (PLL) can be implemented if the synthesizer is used
with external loop filters and voltage controlled oscillators (VCOs).
Control of all the on-chip registers is via a simple 3-wire
interface with 1.8 V compatibility. The devices operate with a
power supply ranging from 2.7 V to 3.3 V and can be powered
down when not in use.
P
1
FREQUENCY
DETECTOR
FREQUENCY
IF PHASE
DETECTOR
RF PHASE
V
P
2
DETECT
DETECT
LOCK
LOCK
RF
IF
IN
Frequency Synthesizer
RFCP3 RFCP2
IFCP3 IFCP2
frequencies at the PFD input. A complete phase-
R
FL
SET
©2002–2010 Analog Devices, Inc. All rights reserved.
REFERENCE
REFERENCE
REFERENCE
IF CURRENT
O
CHARGE
CHARGE
SETTING
OUTPUT
PUMP
SWITCH
PUMP
R
MUX
Dual Low Power PLL
SET
RFCP1
IFCP1
CP
MUXOUT
CP
FL
IF
RF
O
ADF4212L
www.analog.com

Related parts for ADF4212LBCP-REEL7

ADF4212LBCP-REEL7 Summary of contents

Page 1

FEATURES I total: 7 Bandwidth RF/IF: 2.4 GHz/1.0 GHz 2 3.3 V power supply Separate V allows extended tuning voltage P Programmable dual modulus prescaler RF and IF: 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents ...

Page 2

ADF4212L TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin ...

Page 3

SPECIFICATIONS 2 3 otherwise noted; dBm referred to 50 Ω. Table 1. 1 Parameter RF/IF CHARACTERISTICS RF Input Frequency (RF ) ...

Page 4

ADF4212L 2 3 otherwise noted; dBm referred Table 2. 1 Parameter B Version NOISE CHARACTERISTICS 3 RF Phase ...

Page 5

TIMING CHARACTERISTICS 2 3 otherwise noted; dBm referred to 50 Ω. Table 3. 1 Parameter Limit MIN ...

Page 6

ADF4212L ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table Parameter GND GND ...

Page 7

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADF4212L DGND 4 TOP VIEW RF (Not to Scale AGND REF 8 IN DGND 9 IF ...

Page 8

ADF4212L Pin No. Mnemonic TSSOP LFCSP Description Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane DD should be placed as close as possible to this pin ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS –5 –10 –15 –20 –25 –30 0 500 1000 1500 FREQUENCY (MHz) Figure 5. Input Sensitivity (RF Input –5 ...

Page 10

ADF4212L 3V, V REFERENCE DD – 5mA LEVEL = –7.0dBm CP PFD FREQUENCY = 200kHz –20 LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1Hz –30 VIDEO BANDWIDTH = 1Hz SWEEP = 2.5 SECONDS –40 AVERAGES ...

Page 11

TUNING VOLTAGE (V) Figure 17. RF Reference Spurs (200 kHz) vs. V TUNE 0 –20 –40 –60 –80 –100 –120 TUNING VOLTAGE (V) Figure 18. IF ...

Page 12

ADF4212L 0 –20 –40 –60 –80 –100 –120 –40 – TEMPERATURE (°C) Figure 23. RF Spurs vs. Temperature 0 –20 –40 –60 –80 –100 –120 –40 – TEMPERATURE (°C) Figure 24. IF Spurs vs. ...

Page 13

CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 26. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures ...

Page 14

ADF4212L PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure simplified schematic. The PFD ...

Page 15

Table 7. Latch Summary IF CP CURRENT SETTING DB23 DB22 DB21 DB20 DB19 DB18 DB17 IFCP2 IFCP1 IFCP0 PRESCALER DB23 DB22 DB21 DB20 DB19 DB18 DB17 B12 B11 B10 RF CP ...

Page 16

ADF4212L IF R COUNTER LATCH Table Counter Latch Map IF CP CURRENT SETTING DB23 DB22 DB21 DB20 DB19 DB18 DB17 IFCP2 IFCP1 IFCP0 P12 P11 P4 FROM ...

Page 17

IF N COUNTER LATCH Table Counter Latch Map IF PRESCALER DB23 DB22 DB21 DB20 DB19 DB18 DB17 B12 B11 B10 P6 P5 PRESCALER VALUE 16/ 32/33 ...

Page 18

ADF4212L RF R COUNTER LATCH Table 10 Counter Latch Map RF CP CURRENT SETTING DB23 DB22 DB21 DB20 DB19 DB18 DB17 RFCP2 RFCP1 RFCP0 P12 P11 P10 P10 0 1 P12 P11 P4 FROM ...

Page 19

RF N COUNTER LATCH Table 11 Counter Latch Map RF PRESCALER DB23 DB22 DB21 DB20 DB19 DB18 DB17 P17 P16 P15 P14 B12 B11 B10 P15 P14 PRESCALER VALUE 16/ 32/33 ...

Page 20

ADF4212L PROGRAM MODES Table 8 and Table 10 show how to set up the program modes in the ADF4212L. The following should be noted: • IF and RF analog lock detect indicate when the PLL is in lock. When the ...

Page 21

IF Power-Down Table 9 shows the power-down bits in the ADF4212L. IF Fastlock The IF CP gain bit (P8) of the IF N counter latch register in the ADF4212L is the fastlock enable bit. Only when P8 is set to ...

Page 22

ADF4212L APPLICATIONS INFORMATION LOCAL OSCILLATOR FOR GSM HANDSET RECEIVER Figure 31 shows the ADF4212L being used with a VCO to pro- duce the required LOs for a GSM base station transmitter or receiver. The reference input signal is applied to ...

Page 23

WIDEBAND PLL Many of the wireless applications for synthesizers and VCOs in PLLs are narrow band in nature. These applications include the various wireless standards such as GSM, DSC1800, CDMA, or WCDMA. In each of these cases, the total tuning ...

Page 24

ADF4212L INTERFACING The ADF4212L has a simple SPI-compatible interface for writing to the device. CLK, DATA, and LE control the data transfer. When latch enable (LE) goes high, the 22 bits that have been clocked into the input register on ...

Page 25

OUTLINE DIMENSIONS COPLANARITY PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 6.60 6.50 6. 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.30 0.19 SEATING 0.10 PLANE ...

Page 26

... ADF4212LBRUZ-RL −40°C to +85°C ADF4212LBRUZ-RL7 −40°C to +85°C ADF4212LBCPZ −40°C to +85°C ADF4212LBCPZ-RL −40°C to +85°C ADF4212LBCPZ-RL7 −40°C to +85° RoHS Compliant Part. Package Description 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead LFCSP_VQ ...

Page 27

NOTES Rev Page ADF4212L ...

Page 28

ADF4212L NOTES ©2002–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02774-0-11/10(C) Rev Page ...

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