MAX9451EHJ+ Maxim Integrated Products, MAX9451EHJ+ Datasheet - Page 4

• Manufacturer Part Number: MAX9451EHJ+
• Description: IC CLOCK GEN W/VCXO 32-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Clock Generatorr

Specifications of MAX9451EHJ+

• Pll: Yes
• Input: LVCMOS, LVDS, LVPECL
• Output: HSTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP Exposed Pad, 32-eTQFP, 32-HTQFP, 32-VQFP
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Precision Clock Generators
with Integrated VCXO
SERIAL I
(V DD = 2.4V to 3.6V, T A = -40°C to +85°C. See Figure 4 for the timing parameters definition.)
SERIAL SPI INTERFACE TIMING CHARACTERISTICS
(V DD = 2.4V to 3.6V, T A = -40°C to +85°C. See Figure 7 for the timing parameters definition.)
4
Note 1: All timing AC electrical characteristics and timing specifications are guaranteed by design and not production tested.
Note 2: The VCXO tracks the input clock frequency by ±60ppm.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined regions of SCL’s
Note 4: C
Note 5: Input filters on SDA and SCL suppress noise spikes less than 50ns.
Serial Clock
Bus Free Time Between STOP and
START Conditions
Rep eated H ol d Ti m e S TART C ond i ti on
Rep eated S TART C ond i ti on S etup Ti m e
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Clock-Low Period
SCL Clock-High Period
Maximum Receive SCL/SDA Rise Time
Minimum Receive SCL/SDA Rise Time
Maximum Receive SCL/SDA Fall Time
Minimum Receive SCL/SDA Fall Time
Fall Time of SDA, Transmitting
Pulse Width of Suppressed Spike
Capacitive Load for Each Bus Line
Serial-Clock Frequency
CS Fall to CLK Rise Setup Time
DIN Setup Time
DIN Hold Time
CLK High to CS High
CS Pulse-High Time
_______________________________________________________________________________________
falling edge.
B
= total capacitance of one bus line in pF. Tested with C
PARAMETER
2
PARAMETER
C-COMPATIBLE INTERFACE TIMING CHARACTERISTICS
SYMBOL
SYMBOL
t
t
t
t
t
HD,STA
SU,STO
HD,DAT
SU,DAT
SU,STA
t
t
t
t
f
t
HIGH
t
f
t
LOW
CSW
CSS
t
t
CSH
SCL
BUF
F,TX
t
C
SCL
t
t
DS
DH
t
t
SP
R
R
F
F
B
(Note 3)
(Note 4)
(Note 4)
(Note 4)
(Note 5)
(Note 4)
CONDITIONS
CONDITIONS
B
= 400pF.
+ 0.1C
MIN
12.5
12.5
MIN
100
100
1.3
0.6
0.6
0.6
1.3
0.7
20
20
0
0
0
b
+ 0.1 x C
+ 0.1 x C
TYP
TYP
300
300
20
20
b
b
MAX
MAX
400
250
400
50
2
UNITS
UNITS
MHz
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
pF
ns
ns
ns
ns
ns