MAX9451EHJ+ Maxim Integrated Products, MAX9451EHJ+ Datasheet - Page 12

• Manufacturer Part Number: MAX9451EHJ+
• Description: IC CLOCK GEN W/VCXO 32-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Clock Generatorr

Specifications of MAX9451EHJ+

• Pll: Yes
• Input: LVCMOS, LVDS, LVPECL
• Output: HSTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP Exposed Pad, 32-eTQFP, 32-HTQFP, 32-VQFP
• Frequency-max: 160MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Precision Clock Generators
with Integrated VCXO
Figure 6. SMBus Read Timing Diagram
The SPI interface is activated when AD0 = AD1 = high.
The SPI port is a write-only interface, and it uses the
three inputs: CS, SCL, and SDA. Bit D15 is always zero,
indicating the write-only mode, as shown in Figure 5.
D14–D8 are the register address bits and D7–D0 are
the data bits. In Table 4, the register address mapping
is still valid, except the first address bit on the left is not
used. D14 is the MSB of the address, and D7 is the
MSB of the data. D15–D0 are sent with MSB (D15) first.
The maximum SCL frequency is 2MHz.
Figure 7. SPI Write Operation Timing Diagram
Figure 8. SPI Register Address and Data Configuration Function Setting Tables
12
______________________________________________________________________________________
SCLK
SLK
SMBCLK
SMBDATA
SDA
DIN
CS
CS
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
D15
t
SU:STA
A
D14
t
HD:STA
D13
t
LOW
B
t
HIGH
REGISTER ADDRESS
D12
t
t
DS
CSS
D15
t
DS
D11
t
SU:DAT
SPI Interface
C
D10
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = MASTER PULLS DATA LINE LOW
D14
D9
D
D8
E
F
D7
To perform a write, set D15 = 0, drive CS low, toggle
SCL to latch SDA data on the rising edge, then drive
CS high after 16 SCL cycles for two SCL cycles to sig-
nal the boundary of a 16-bit word (Figure 5). SCL must
be low when CS falls at the start of a transmission.
Switching of SCL and SDA is ignored unless CS is low.
Figure 7 shows the SPI write operation timing diagram
and Figure 8 shows SPI register address and data con-
figuration function setting tables.
t
HD:DAT
D1
D6
G
D5
f
SCL
D4
D0
H
REGISTER DATA
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
D3
t
CSH
I
J K
D2
t
CSW
D1
t
D0
SU:STO
L
t
BUF
M