FS6377-01G-XTP ON Semiconductor, FS6377-01G-XTP Datasheet - Page 18

• Manufacturer Part Number: FS6377-01G-XTP
• Description: IC CLOCK GEN PLL PROG 16SOIC
• Manufacturer: ON Semiconductor
• Type: PLL Clock Generatorr

Specifications of FS6377-01G-XTP

• Pll: Yes
• Input: Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Frequency - Max: 230MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FS6377
Table 13: AC Timing Specifications
Parameter
Overall
Output frequency*
VCO frequency*
VCO gain*
Loop filter time constant*
Rise time*
Fall time*
Tristate enable delay*
Tristate disable delay*
Clock stabilization time*
Divider Modulus
Feedback divider
Reference divider
Post divider
Clock Outputs (PLL A clock via CLK_A pin) Approximate
Duty cycle*
Jitter, long term (σy(τ))*
Jitter, period (peak-peak)*
Clock Outputs (PLL B clock via CLK_B pin) Approximate
Duty cycle*
Jitter, long term (σy(τ))*
Jitter, period (peak-peak)*
Symbol
f
f
A
t
t
t
t
t
N
N
N
t
t
t
t
O
VCO
r
r
PZL
PZL
STB
j(LT)
j(ΔP)
j(LT)
j(ΔP)
VCO
F
R
P
, t
, t
PZH
PZH
Conditions/Descriptions
V
V
V
V
LFTC bit = 0
LFTC bit = 1
V
V
V
V
Output active from power-up, via PD pin
After last register is written
See Table 2
See Table 8
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
On rising edges 500µs apart at 2.5V relative to an
ideal clock, C
N
On rising edges 500µs apart at 2.5V relative to an
ideal clock, C
N
C = 40MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
C
N
From rising edge to the next rising edge at 2.5V,
C
N
C = 40MHz, D = 14.318MHz)
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
On rising edges 500µs apart at 2.5V relative to an
ideal clock, C
N
On rising edges 500µs apart at 2.5V relative to an
ideal clock, C
N
C = 40MHz, D = 14.318MHz)
From rising edge to the next rising edge at 2.5V,
C
N
From rising edge to the next rising edge at 2.5V,
C
N
C = 40MHz, D = 14.318MHz)
DD
DD
DD
DD
O
O
O
O
R
R
L
PX
L
PX
R
R
L
PX
L
PX
= 15pF, f
= 15pF, f
= 15pF, f
= 15pF, f
= 0.5V to 4.5V; C
= 0.3V to 3.0V; C
= 4.5V to 0.5V; C
= 3.0V to 0.3V; C
= 63, N
= 63, N
= 63, N
= 63, N
= 5.5V
= 3.6V
= 5.5V
= 3.6V
= 50, no other PLLs active
= 50, all other PLLs active (B = 60MHz,
= 50, no other PLLs active
= 50, all other PLLs active (A = 50MHz,
PX
PX
PX
PX
XIN
XIN
XIN
XIN
Rev. 4 | Page 18 of 24 | www.onsemi.com
= 50, no other PLLs active
= 50, no other PLLs active
= 50, all other PLLs active (B = 60MHz,
= 50, all other PLLs active (A = 50MHz,
L
L
L
L
= 14.318MHz, N
= 14.318MHz, N
= 14.318MHz, N
= 14.318MHz, N
= 15pF, f
= 15pF, f
= 15pF, f
= 15pF, f
L
L
L
L
= 15pF
= 15pF
= 15pF
= 15pF
XIN
XIN
XIN
XIN
= 14.318MHz, N
= 14.318MHz, N
= 14.318MHz, N
= 14.318MHz, N
F
F
F
F
= 220, N
= 220, N
= 220, N
= 220, N
R
R
R
R
= 63,
= 63,
= 63,
= 63,
F
F
F
F
= 220,
= 220,
= 220,
= 220,
Clock
(MHz)
100
100
100
100
100
100
50
50
60
60
Min.
0.8
0.8
40
40
45
45
1
1
8
1
1
Typ.
400
100
165
110
390
120
400
1.9
1.6
1.8
1.5
20
45
45
75
7
2047
Max.
150
100
230
170
255
50
55
55
8
8
1
MHz/V
Units
MHz
MHz
ms
µs
ns
ns
ns
ns
µs
ps
ps
ps
ps
%
%