IDTQS5917T-132TJ8 IDT, Integrated Device Technology Inc, IDTQS5917T-132TJ8 Datasheet

no-image

IDTQS5917T-132TJ8

Manufacturer Part Number
IDTQS5917T-132TJ8
Description
IC CLOCK GEN LVTTL 132MHZ 28PLCC
Manufacturer
IDT, Integrated Device Technology Inc
Type
Driver, PLLr
Datasheet

Specifications of IDTQS5917T-132TJ8

Pll
Yes with Bypass
Input
Clock
Output
LVCMOS, TLL, 3-State
Number Of Circuits
1
Ratio - Input:output
2:8
Differential - Input:output
No/No
Frequency - Max
132MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Frequency-max
132MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
QS5917T-132TJ8

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDTQS5917T-132TJ8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
FEATURES:
• 5V operation
• 2xQ output, Q/2 output, Q output
• Outputs tri-state while RST low
• Internal loop filter RC network
• Low noise TTL level outputs
• < 500ps output skew, Q
• PLL disable feature for low frequency testing
• Balanced Drive Outputs ± 24mA
• 132MHz maximum frequency (2xQ output)
• Functional equivalent to Motorola MC88915
• ESD > 2000V
• Latch-up > –300mA
• Available in QSOP and PLCC packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2006 Integrated Device Technology, Inc.
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
RST
R
Q/2
Q
D
SYNC
SYNC
0
1
R
0
-Q
4
Q
Q
5
D
REF_SEL
0
1
R
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
Q
Q
4
DETECTOR
D
LOCK
PHASE
R
FEEDBACK
Q
Q
3
1
D
DESCRIPTION
to lock low skew outputs to one of two reference clock inputs. Eight
outputs are available: Q
insures < 500ps skew between the Q
includes an internal RC filter which provides excellent jitter characteris-
tics and eliminates the need for external components. In addition, TTL
level outputs reduce clock signal noise. Various combinations of feed-
back and a divide-by-2 in the VCO path allow applications to be custom-
ized for linear VCO operation over a wide range of input SYNC fre-
quencies. The VCO can also be disabled by the PLL_EN signal to allow
low frequency or DC testing. The LOCK output asserts to indicate when
phase lock has been achieved. The QS5917T is designed for use in
high-performance workstations, multi-board computers, networking hardware,
and mainframe systems. Several can be used in parallel or scattered
throughout a system for guaranteed low skew, system-wide clock distri-
bution networks.
Note AN-227.
FILTER
LOOP
The QS5917T Clock Driver uses an internal phase locked loop (PLL)
For more information on PLL clock driver products, see Application
R
Q
Q
2
VCO
D
0
-Q
R
4
, 2xQ, Q/2, Q
PLL_EN
INDUSTRIAL TEMPERATURE RANGE
Q
Q
1
0
1
0
-Q
D
4
, and Q/2 outputs. The QS5917T
SEPTEMBER 2006
5
. Careful layout and design
/2
Q
R
Q
0
FREQ_SEL
1
0
QS5917T
D
Q
DSC-5227/4
2xQ

Related parts for IDTQS5917T-132TJ8

IDTQS5917T-132TJ8 Summary of contents

Page 1

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • 5V operation • 2xQ output, Q/2 output, Q output • Outputs tri-state while RST low • Internal loop filter RC network • Low noise TTL level outputs ...

Page 2

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN CONFIGURATION 1 GND RST FEEDBACK 5 REF_SEL 6 SYNC AGND 10 SYNC 11 1 ...

Page 3

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN DESCRIPTION Pin Names I/O SYNC I Reference clock input 0 SYNC I Reference clock input 1 REF_SEL I Reference clock select. When 1, selects SYNC FREQ_SEL I VCO ...

Page 4

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FREQUENCY SELECTION TABLE Output Used for FREQ_SEL Feedback 1 Q 2xQ 0 Q ...

Page 5

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INPUT TIMING REQUIREMENTS Symbol Maximum input rise and fall times, 0. Input Clock Frequency, SYNC I t Input clock pulse, HIGH ...

Page 6

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER TEST LOAD V DD 160Ω OUTPUT 68Ω TEST CIRCUIT 1 PLL OPERATION The Phase Locked Loop (PLL) circuit included in the QS5917T provides for replication of incoming SYNC clock ...

Page 7

QS5917T LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER ORDERING INFORMATION QS XXXX XX Speed Device Type Package CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X X Process Blank -70T ...

Related keywords