MK1574-01SILFTR IDT, Integrated Device Technology Inc, MK1574-01SILFTR Datasheet - Page 5

• Manufacturer Part Number: MK1574-01SILFTR
• Description: IC PLL FRAME RATE COMM 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Frequency Synthesizerr

Specifications of MK1574-01SILFTR

• Pll: Yes
• Input: Clock
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Divider/multiplier: No/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -

AC Electrical Characteristics
Thermal Characteristics
Loop Bandwidth and Loop Filter Component Selection
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
VDD = 3.3 V, Ambient Temperature 0 to +70°C, unless stated otherwise
Note 1: All multipliers as shown in the table on page two are exact, and are stored in ROM on the chip.
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic characteristics of
the phase-locked loop. The capacitor must have very low leakage, therefore a high quality ceramic capacitor is
recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic capacitors should have C0G or
NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other ceramics which have piezoelectric
properties allow mechanical vibration in the system to increase the output jitter because the mechanical energy is
converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components are
calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7). The loop bandwidth is set
by the capacitor C and the constant K1 using the formula:
BW (Hz) =
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle,
High time
Absolute Clock Period
Jitter
Actual Mean Frequency
Error Versus Target (note
1)
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Parameter
K1
C
Parameter
Symbol
Equation 1
t
t
t
f
OR
DC
OF
IN
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2
Any clock selection
Symbol
θ
θ
θ
θ
JA
JA
JA
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
5
Conditions
Min.
Min.
40
1
49 to 51
8.000
Typ.
Typ.
120
115
105
58
0
MK1574
CLOCK SYNTHESIZER
Max. Units
Max. Units
1.5
1.5
60
0
°C/W
°C/W
°C/W
°C/W
ppm
kHz
ns
ns
ns
%
REV F 111605