MK1574-01SILFTR IDT, Integrated Device Technology Inc, MK1574-01SILFTR Datasheet - Page 3
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MK1574-01SILFTR
Manufacturer Part Number
MK1574-01SILFTR
Description
IC PLL FRAME RATE COMM 16-SOIC
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock/Frequency Synthesizerr
Datasheet
1.MK1574-01SLFTR.pdf
(10 pages)
Specifications of MK1574-01SILFTR
Pll
Yes
Input
Clock
Output
CMOS
Number Of Circuits
1
Ratio - Input:output
1:3
Differential - Input:output
No/No
Divider/multiplier
No/Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency-max
-
Pin Descriptions
External Components
IDT™ / ICS™ 3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Number
MK1574
3.3 VOLT FRAME RATE COMMUNICATIONS PLL
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
The MK1574 requires a minimum number of external components for proper operation. An RC network (see the
section “Loop Bandwidth and Loop Filter Component Selection”) should be connected between CAP1 and CAP2 as
close tot he device as possible. Decoupling capacitors of 0.01µF should be connected between VDD and GND on
pins 2, 3, 5 and 7, as close to the device as possible. A series termination resistor of 33Ω may be used close to
each clock output pin to reduce reflections.
8KOUT
Name
CAP1
CAP2
CLK1
CLK2
CLK3
ICLK
GND
GND
VDD
VDD
FS0
FS1
FS2
FS3
Pin
NC
Output Recovered 8 kHz output clock. Can be low jitter, better duty cycle than clock
Output Clock 1 determined by status of FS3:0 per table above.
Output Clock 2 determined by status of FS3:0 per table above.
Output Clock 3 determined by status of FS3:0 per table above.
Power
Power
Power
Power
Power
Type
Input
Input
Input
Input
Input
Input
Pin
—
Clock input. Connect to an 8 kHz clock input.
Connect to 3.3 V.
Connect to 3.3 V.
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP2. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
Connect to ground.
Connect to a ceramic capacitor and a resistor in series between this pin and
CAP1. Refer to the section “Loop Bandwidth and Loop Filter Component
Selection”.
Connect to ground.
Frequency select 0. Determines CLK outputs per table above.
input.
Frequency select 1. Determines CLK outputs per table above.
Frequency select 2. Determines CLK outputs per table above.
No connect. Do not connect anything to this pin.
Frequency select 3. Determines CLK outputs per table above.
3
Pin Description
MK1574
CLOCK SYNTHESIZER
REV F 111605