AD9552BCPZ Analog Devices Inc, AD9552BCPZ Datasheet - Page 8

• Manufacturer Part Number: AD9552BCPZ
• Description: IC PLL CLOCK GEN LP 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generatorr

Specifications of AD9552BCPZ

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/Yes
• Frequency - Max: 900MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 900MHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial, SPI
• Frequency: 112.5MHz
• No. Of Outputs: 2
• Supply Current: 149mA
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 3.135V To 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9552
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
29, 30, 31,
32, 1, 2
3, 4, 5
6
7, 18, 21, 28
8, 17, 19
9, 10
11
12
13
14
15
16
20
26, 22
27, 23
24, 25
EP
1
I = input, I/O = input/output, O = output, P = power, P/O = power/output.
Mnemonic
Y0, Y1, Y2, Y3, Y4,
Y5
A0, A1, A2
RESET
VDD
LDO
XTAL
REF
CS
SCLK
SDIO
OUTSEL
FILTER
LOCKED
OUT1, OUT2
OUT1, OUT2
GND
Exposed Die Pad
Type
I
I
I
P
P/O
I
I
I
I
I/O
I
I/O
O
O
O
P
1
Description
Control Pins. These pins select preset values for the PLL feedback divider and the OUT1
dividers based on the input reference frequency selected via the A[0:2] pins and have
internal 100 kΩ pull-up resistors.
Control Pins. These pins select the input reference frequency and have internal 100 kΩ pull-
up resistors.
Digital Input, Active High. Resets internal logic to default states. This pin has an internal
100 kΩ pull-up resistor, so the default state of the device is reset.
Power Supply Connection: 3.3 V Analog Supply.
LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to
ground.
Crystal Resonator Input. Connect a crystal resonator across these pins.
Reference Clock Input. Connect this pin to an active clock input signal, or connect it to VDD
when using a crystal resonator across the XTAL pins.
Digital Input, Active Low, Chip Select.
Serial Data Clock.
Digital Serial Data Input/Output.
Logic 0 selects LVDS and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2
when the outputs are not under SPI port control. Can be overridden via the programming
registers. This pin has an internal 100 kΩ pull-up resistor.
Loop Filter Node for the PLL. Connect an external 12 nF capacitor from this pin to Pin 17 (LDO).
Active High Locked Status Indicator for the PLL.
Complementary Square Wave Clocking Outputs.
Square Wave Clocking Outputs.
Analog Ground.
The exposed die pad must be connected to GND.
RESET
NOTES
1. EXPOSED DIE PAD MUST BE
CONNECTED TO GND.
VDD
LDO
A0
A1
A2
Y4
Y5
1
2
3
4
5
6
7
8
Figure 2. Pin Configuration
Rev. C | Page 8 of 32
(Not to Scale)
PIN 1
INDICATOR
AD9552
TOP VIEW
24 GND
23 OUT2
22
21 VDD
20 LOCKED
19 LDO
18 VDD
17 LDO
OUT2