AD9552BCPZ Analog Devices Inc, AD9552BCPZ Datasheet - Page 3

• Manufacturer Part Number: AD9552BCPZ
• Description: IC PLL CLOCK GEN LP 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generatorr

Specifications of AD9552BCPZ

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/Yes
• Frequency - Max: 900MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 900MHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial, SPI
• Frequency: 112.5MHz
• No. Of Outputs: 2
• Supply Current: 149mA
• Digital Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 3.135V To 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 3.3 V; T
Table 1.
Parameter
SUPPLY VOLTAGE
POWER CONSUMPTION
LOGIC INPUT PINS
LOGIC OUTPUT PINS
RESET PIN
REFERENCE CLOCK
INPUT CHARACTERISTICS
Total Current
VDD Current By Pin
LVPECL Output Driver
INPUT CHARACTERISTICS
Output Characteristics
Input Characteristics
Minimum Pulse Width High
Frequency Range
Pin 7
Pin 18
Pin 21
Pin 28
Logic 1 Voltage, V
Logic 0 Voltage, V
Logic 1 Current, I
Logic 0 Current, I
Output Voltage High, V
Output Voltage Low, V
Input Voltage High, V
Input Voltage Low, V
Input Current High, I
Input Current Low, I
IH
IL
IH
IL
2
INL
IL
INH
IH
OL
1
OH
A
3.135
Min
1.0
2.7
1.8
2
7.94
6.57
= 25°C, unless otherwise noted.
Typ
3.30
149
2
77
35
35
36
0.3
31
Max
3.465
169
3
86
41
41
41
0.8
3
17
0.4
1.3
12.5
43
93.06
71.28
112.5
86.17
Unit
V
mA
mA
mA
mA
mA
mA
V
V
μA
μA
V
V
V
V
μA
μA
ns
MHz
MHz
MHz
MHz
MHz
MHz
Rev. C | Page 3 of 32
Test Conditions/Comments
Pin 7, Pin 18, Pin 21, Pin 28
At maximum output frequency with both output channels active
900 MHz with 100 Ω termination between both pins of the output
driver
For the CMOS inputs, a static Logic 1 results from either a pull-up
resistor or no connection
N
N
strains the frequency at OUT1 to be an integer sub-multiple of 3.35 GHz
(that is, f
output divider values)
SDM
SDM
SDM
frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is,
f
divider values)
SDM
at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, f
4.05÷M GHz, where M is the product of the P
values)
OUT1
3
3
= 255; 2× frequency multiplier enabled; valid for all VCO bands
= 255; 2× frequency multiplier enabled; f
4
4
= 4.05÷M GHz, where M is the product of the P
4
4
disabled; N
enabled; N
enabled; N
disabled; N
OUT1
= 3.35 ÷ M GHz, where M is the product of the P
3
3
3
= 47
= 47
= 36
3
= 36
6
6
5
; valid for all VCO bands
; valid for all VCO bands
; f
5
; f
VCO
VCO
= 4.05 GHz, which constrains the frequency
= 4.05 GHz, which constrains the
VCO
0
and P
= 3.35 GHz, which con-
0
1
and P
output divider
1
AD9552
OUT1
output
0
and P
=
1