CY2305CSXC-1H Cypress Semiconductor Corp, CY2305CSXC-1H Datasheet - Page 5

• Manufacturer Part Number: CY2305CSXC-1H
• Description: IC CLK ZDB 5OUT 133MHZ 8SOIC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY2305CSXC-1H

• Number Of Circuits: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Pll: Yes
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 1:5
• Differential - Input:output: No/No
• Frequency - Max: 133.33MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 133MHz
• Output Frequency Range: 10 MHz to 133.33 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2194-5; CY2305CSXC-1H

Document Number: 38-07672 Rev. *K
Table 2. Pin Definition - 16 Pin SOIC/TSSOP (continued)
Table 3. Select Input Decoding for CY2309C
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input or output delay.
For applications requiring zero input or output delay, all outputs
including CLKOUT are equally loaded. Even if CLKOUT is not
Notes
4. Weak pull ups on these inputs.
5. Weak pull down on all outputs.
6. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
S2
0
0
1
1
Pin
10
11
12
13
14
15
16
9
S1
0
1
0
1
S1
CLKB3
CLKB4
GND
V
CLKA3
CLKA4
CLKOUT
DD
[4]
CLOCK A1–A4
[5]
[5]
[5]
[5]
Three state
[5]
Signal
Driven
Driven
Driven
CLOCK B1–B4
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3 V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered output, internal feedback on this pin
Three state
Three state
Driven
Driven
CLKOUT
used, it must have a capacitive load equal to that on other
outputs for obtaining zero input or output delay.
For zero output to output skew, all outputs must be loaded
equally.
Driven
Driven
Driven
Driven
[6]
Description
Output Source
Reference
PLL
PLL
PLL
PLL Shutdown
CY2305C
CY2309C
N
N
N
Y
Page 5 of 17
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