ADF4106BCPZ Analog Devices Inc, ADF4106BCPZ Datasheet - Page 9

• Manufacturer Part Number: ADF4106BCPZ
• Description: IC PLL FREQ SYNTHESIZER 20LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4106BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 6GHz
• Pll Type: Frequency Synthesis
• Frequency: 6GHz
• Supply Current: 13mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4106EBZ1 - BOARD EVAL FOR ADF4106
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

GENERAL DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is a normally open switch.
When power-down is initiated, SW3 is closed and SW1 and
SW2 are opened. This ensures that there is no loading of the
REF
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
PRESCALER (P/P +1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A counter and
B counter. The prescaler is programmable. It can be set in soft-
ware to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value, and is given by (P
RF
RF
IN
IN
IN
pin on power-down.
REF
A
B
IN
GENERATOR
NC
POWER-DOWN
Figure 17. Reference Input Stage
BIAS
SW1
CONTROL
Figure 18. RF Input Stage
NO
NC
500Ω
SW2
SW3
100kΩ
1.6V
500Ω
2
BUFFER
− P).
AGND
AV
DD
TO R COUNTER
Rev. C | Page 9 of 24
A COUNTER AND B COUNTER
The A counter and B CMOS counter combine with the dual
modulus prescaler to allow a wide ranging division ratio in the
PLL feedback counter. The counters are specified to work when
the prescaler output is 325 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is
where:
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.
INPUT STAGE
f
P is the preset modulus of the dual-modulus prescaler
B is the preset divide ratio of the binary 13-bit counter
A is the preset divide ratio of the binary 6-bit swallow
f
VCO
REFIN
FROM RF
oscillator (VCO).
(8/9, 16/17, etc.).
(3 to 8191).
counter (0 to 63).
f
VCO
is the output frequency of the external voltage controlled
is the external reference frequency oscillator.
=
[
(
P
MODULUS
N DIVIDER
CONTROL
×
N = BP + A
B
)
PRESCALER
+
A
P/P + 1
Figure 19. A and B Counters
]
×
f
REFIN
R
LOAD
LOAD
COUNTER
COUNTER
13-BIT B
6-BIT A
ADF4106
TO PFD