ADF4106BCPZ Analog Devices Inc, ADF4106BCPZ Datasheet - Page 18

• Manufacturer Part Number: ADF4106BCPZ
• Description: IC PLL FREQ SYNTHESIZER 20LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4106BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-LFCSP
• Frequency-max: 6GHz
• Pll Type: Frequency Synthesis
• Frequency: 6GHz
• Supply Current: 13mA
• Supply Voltage Range: 2.7V To 3.3V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 20
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4106EBZ1 - BOARD EVAL FOR ADF4106
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4106
APPLICATIONS
LOCAL OSCILLATOR FOR LMDS BASE STATION
TRANSMITTER
Figure 22 shows the ADF4106 being used with a VCO to
produce the LO for an LMDS base station.
The reference input signal is applied to the circuit at FREF
and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
reference input without any 50 Ω termination.
To achieve a channel spacing of 1 MHz at the output, the
10 MHz reference input must be divided by 10, using the
on-chip reference divider of the ADF4106.
The charge pump output of the ADF4106 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for
the system would be 45°.
Other PLL system specifications include:
K
K
D
V
= 2.5 mA
= 80 MHz/V
FREF
IN
1000pF
51Ω
5.1kΩ
1000pF
1
8
CE
CLK
DATA
LE
AV
REF
3
R
V
7
SET
DD
DD
ADF4106
IN
4
DV
Figure 22. Local Oscillator for LMDS Base Station
MUXOUT
15
DD
9
RF
RF
IN
IN
CP
V
V
16
A
B
P
P
14
2
6
5
IN
Rev. C | Page 18 of 24
100pF
100pF
100pF
LOCK
DETECT
NOTE
DECOUPLING CAPACITORS (0.1
V
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
P
OF THE ADF4106 AND ON V
51Ω
These specifications are needed and used to derive the loop
filter component values shown in Figure 22.
The circuit in Figure 22 shows a typical phase noise
performance of −83.5 dBc/Hz at 1 kHz offset from the carrier.
Spurs are better than −62 dBc.
The loop filter output drives the VCO, which in turn is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RF
terminal of the synthesizer.
In a PLL system, it is important to know when the system
is in lock. In Figure 22, this is accomplished by using the
MUXOUT signal from the synthesizer. The MUXOUT pin
can be programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock-detect signal.
4.3kΩ
1.5nF
6.2kΩ
Loop Bandwidth = 50 kHz
F
N = 5800
Extra Reference Spur Attenuation = 10 dB
PFD
= 1 MHz
20pF
2
V956ME03
V
CC
14
CC
μ
F/10pF) ON AV
OF THE V956ME03 HAVE
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
10
100pF
DD
, DV
100pF
18Ω
DD
, AND
18Ω
18Ω
RF
OUT
IN