MB15U36PFV-G-BNDE1 Fujitsu Semiconductor America Inc, MB15U36PFV-G-BNDE1 Datasheet - Page 14

• Manufacturer Part Number: MB15U36PFV-G-BNDE1
• Description: SYNTHESIZER PLL DUAL INP 20SSOP
• Manufacturer: Fujitsu Semiconductor America Inc
• Type: Clock/Frequency Synthesizer (RF/IF), Prescalerr

Specifications of MB15U36PFV-G-BNDE1

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 2GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Frequency-max: 2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1005-2

Dual PLL Frequency Synthesizer with On-Chip Prescaler
Functional Descriptions
The VCO output frequency can be calculated using the following equation:
f
f
M:
N:
A:
f
R:
Serial Data Input
Serial data is entered using the Data, Clock, and LE pins. The serial data controls the programmable reference counters and the programmable
counters separately.
Binary serial data is entered through the Data pin when the LE pin is held low. One bit of data is shifted into the shift register on the rising
edge of the Clock. When the LE signal pin is taken high, entered data is latched into the appropriate counters according to the control bit
settings as follows:
Table 1. Control Bits
14
VCO
VCO
OSC
Shift Register Configuration
Programmable Reference Counter
CNT1, 2
R1 to R15
FC
CMC
ZC
LDS/FDS
Note: Input Data with MSB first.
LSB
C
N
1
1
: Reference oscillation frequency
: Output frequency of external voltage controlled oscillator (VCO)
= {(M x N) + A} x f
Fujitsu Microelectronics, Inc.
CN1
Preset divide ratio of dual modulus prescaler (64 or 128 for RF1-PLL or RF2-PLL2)
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
Preset divide ratio of binary 14-bit programmable reference counter (3 to 32,767)
H
H
L
L
C
N
2
2
Control Bits
R
1
3
Control bits
Divide ratio setting bits for the programmable reference counter (3 to 32,767)
Phase control bit for the phase detector
Charge pump current select bit
Forced high impedance control for the charge pump
LD/f
OUT
R
2
4
signal select bits
CN2
R
5
3
H
H
L
L
OSC
÷ R (A < N)
R
6
4
R
7
5
R
8
6
R
9
7
Data Flow
10
R
8
11
R
9
The programmable reference counter for the RF2-PLL
The programmable reference counter for the RF1-PLL
The programmable counter and the swallow counter for the RF2-PLL
The programmable counter and the swallow counter for the RF1-PLL
12
10
R
13
11
R
14
12
R
Destination of Serial Data
[Table 1]
[Table 2]
[Table 3]
[Table 4]
[Table 5]
[Table 6]
15
13
R
16
14
R
17
15
R
18
C
F
19
M
C
C
20
Z
C
21
D
L
S
MSB
22
D
F
S