MPC9443AE Freescale Semiconductor, MPC9443AE Datasheet

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MPC9443AE

Manufacturer Part Number
MPC9443AE
Description
IC CLOCK FANOUT BUFF LV 48-LQFP
Manufacturer
Freescale Semiconductor
Type
Fanout Buffer (Distribution), Divider, Multiplexerr
Datasheet

Specifications of MPC9443AE

Number Of Circuits
1
Ratio - Input:output
2:16
Differential - Input:output
Yes/No
Input
LVCMOS, LVPECL
Output
LVCMOS
Frequency - Max
350MHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Frequency-max
350MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
2.5 V and 3.3 V LVCMOS Clock
Fanout Buffer
designed for low-voltage high-performance telecom, networking and
computing applications. The device supports 3.3 V, 2.5 V and dual supply
voltage (mixed-voltage) applications. The MPC9443 offers 16 low-skew
outputs which are divided into 4 individually configurable banks. Each output
bank can be individually supplied by 2.5 V or 3.3 V, individually set to run at 1X
or 1/2X of the input clock frequency or be disabled (logic low output state). Two
selectable LVPECL compatible inputs support differential clock distribution
systems. In addition, one selectable LVCMOS input is provided for LVCMOS
clock distribution systems. The MPC9443 is specified for the extended
temperature range of –40 to +85°C.
Features
Functional Description
to ensure minimal skew between the four output banks.
In addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be individu-
ally supplied by 2.5 V or 3.3 V, supporting mixed voltage applications. The FSELx pins choose between division of the input reference
frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output banks are in
high-impedance state by deasserting the OE
Impedance Control (OE
compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the
MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at V
in a 7x7 mm
© Motorola, Inc. 2004
The MPC9443 is a 2.5 V and 3.3 V compatible 1:16 clock distribution buffer
The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed on-chip
Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources.
Configurable 16 outputs LVCMOS clock distribution buffer
Output clock frequency up to 350 MHz
Designed for high-performance telecom, networking and computer
applications
Supports applications requiring clock redundancy
Max. output skew of 250 ps (125 ps within one bank)
Selectable output configurations per output bank
Individually per-bank high-impedance tristate
Output disable (stop in logic low state) control
48 ld LQFP package
Ambient operating temperature range of –40 to 85°C
Compatible to single, dual and mixed 3.3 V / 2.5 V voltage supply
2
48-lead LQFP package.
N
) for details. The outputs can be synchronously stopped (logic low state). The outputs provide LVCMOS
N
pins. Asserting OE
N
will the enable output banks. Please see Table 4. Output High-
CLOCK FANOUT BUFFER
2.5 V AND 3.3 V LVCMOS
LOW VOLTAGE SUPPLY
48-LEAD LQFP PACKAGE
CC
MPC9443
= 3.3 V. The device is packaged
CASE 932-03
FA SUFFIX
SCALE 2:1
Order number: MPC9443
Rev 3, 06/2004

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MPC9443AE Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 2.5 V and 3.3 V LVCMOS Clock Fanout Buffer The MPC9443 is a 2.5 V and 3.3 V compatible 1:16 clock distribution buffer designed for low-voltage high-performance telecom, networking and computing applications. The device supports 3.3 ...

Page 2

MPC9443 (PULLDOWN) PCLK0 PCLK0 (PULLUP) (PULLDOWN) PCLK1 PCLK1 (PULLUP) TCLK (PULLDOWN) PCLK_SEL (PULLDOWN) TCLK_SEL (PULLDOWN) FSEL A (PULLDOWN) FSEL B (PULLDOWN) FSEL C (PULLDOWN) FSEL D (PULLDOWN) CLK_STOP (PULLDOWN (PULLDOWN (PULLDOWN) V QA4 QA3 QA2 GND ...

Page 3

Table 1. Pin Configuration Pin CCLK Input PCLK0, PCLK0 Input PCLK1, PCLK1 Input FSEL , FSEL , FSEL , FSEL Input CCLK_SEL Input PCLK_SEL Input Input 0 1 CLK_STOP Input GND V , ...

Page 4

MPC9443 Table 4. Output High-Impedance Control ( QA0 to QA4 Enabled 0 1 Enabled 1 0 Enabled 1 1 Disabled (tristate will tristate (high impedance) output banks independent on the logic state ...

Page 5

Table 7. DC Characteristics ( Symbol Characteristics V Input High Voltage IH V Input Low Voltage IL V Peak-to-Peak Input VoltagePCLK0 Common Mode RangePCLK0 CMR I 2 Input Current IN V Output ...

Page 6

MPC9443 Table 9. DC Characteristics ( Symbol Characteristics V Input High Voltage IH V Input Low Voltage IL V Peak-to-Peak Input VoltagePCLK0 Common Mode RangePCLK0 CMR I 2 Input Current IN V ...

Page 7

Table 11. DC Characteristics (V CC Symbol Characteristics V Input High Voltage IH V Input Low Voltage Input Current IN V Output High Voltage OH V Output Low Voltage OL V Peak-to-Peak Input Voltage PP 3 Common ...

Page 8

MPC9443 Driving Transmission Lines The MPC9443 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. ...

Page 9

Power Consumption of the MPC9443 and Thermal Management The MPC9443 AC specification is guaranteed for the entire operating frequency range up to 350 MHz. The MPC9443 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending ...

Page 10

MPC9443 Figure 6. Maximum MPC9443 frequency, V MTBF 9.1 Years, Driving Series Terminated Transmission Lines Figure 8. Maximum MPC9443 Frequency, V MTBF 4 Years, Driving Series Terminated Transmission Lines MOTOROLA = 3.3 V, Figure 7. Maximum MPC9443 Frequency ...

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Pulse Generator Ω Figure 10. CCLK MPC9443 AC Test Reference for V Differential Pulse Generator Ω PCLK V PP PCLK P(LH) P(HL) Figure 12. Propagation Delay (t t SK(LH) The ...

Page 12

MPC9443 100 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 16. Output ...

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AB T 0.200 AC T BASE METAL 0.080 AC T SECTION AE-AE TIMING SOLUTIONS OUTLINE DIMENSIONS ...

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MPC9443 MOTOROLA NOTES 14 TIMING SOLUTIONS ...

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TIMING SOLUTIONS NOTES 15 MPC9443 MOTOROLA ...

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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the ...

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