NB4L339MNR4G ON Semiconductor, NB4L339MNR4G Datasheet - Page 7

• Manufacturer Part Number: NB4L339MNR4G
• Description: IC CLOCK IN-DIFF LVPECL 32-QFN
• Manufacturer: ON Semiconductor
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of NB4L339MNR4G

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 700MHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NB4L339MNR4G; NB4L339MNR4GOSTR

Application Information
and low skew fan−out buffer featuring a 2:1 Clock
multiplexer front end and outputs a selection of four
different divide ratios; ÷1/2/4/8. One divide block has a
choice of ÷1 or ÷ 2. The outputs of all four divider blocks are
fanned−out to two pair of identical differential LVPECL
copies of the selected clock. All outputs provide standard
LVPECL voltage levels when externally terminated with a
50−ohm resistor to V
50−W termination resistors in a 100−W center−tapped
configuration and are accessible via a VTx pin. This feature
provides transmission line termination on−chip, at the
receiver end, eliminating external components. Inputs
CLKA/B and CLKA/B must be signal driven or auto
oscillation may result.
The NB4L339 is a high−speed, Clock multiplexer, divider
The differential Clock input buffers incorporate internal
Figure 5. Output Voltage Amplitude (V
TT
Figure 4. NB4L339 vs. Agilent 8665A 622.08 MHz at 3.3 V, Room Ambient
= V
800
700
600
500
400
300
200
100
0
CC
0
− 2 V.
0.1
0.2
f
out
0.3
, CLOCK OUTPUT FREQUENCY (GHz)
Ambient Temperature (Typical)
0.4
http://onsemi.com
0.5
OUTPP
0.6
7
differential signal level technologies including LVDS,
LVPECL, or CML.
Therefore, the common output edges are precisely aligned.
internal divider flip−flops will only be enabled/disabled
when the internal clock is in the LOW state. This avoids any
chance of generating a runt pulse on the internal clock when
the device is enabled/disabled, as can happen with an
asynchronous control. The internal enable flip−flop is
clocked on the falling edge of the input clock. Therefore, all
associated specification limits are referenced to the negative
edge of the clock input.
forced LOW, all Q outputs go to logic LOW.
0.7
) vs. Input Clock Frequency (f
The NB4L339 Clock inputs can be driven by a variety of
The internal dividers are synchronous to each other.
The Output Enable pin (EN) is synchronous so that the
The Master Reset (MR) is asynchronous. When MR is
0.8
0.9
1.0
1.1
1.2
in
) at