nb4l339 ON Semiconductor, nb4l339 Datasheet
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nb4l339
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nb4l339 Summary of contents
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... Divider / Fan−Out Buffer Multi−Level Inputs w/ Internal Termination Description The NB4L339 is a multi−function Clock generator featuring a 2:1 Clock multiplexer front end and simultaneously outputs a selection of four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8. One divide block has a choice of ÷1 or ÷ 2. ...
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... H X (Don’t Care Pin will default HIGH when left OPEN Exposed Pad (EP NB4L339 Figure 3. Pinout QFN−32 (Top View) http://onsemi.com 2 QA0 foutA = 622.08 MHz ...
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Table 4. Pin Description Pin Name I − CLKA LVPECL, CML, LVDS Input 3 VTA − 4 CLKA LVPECL, CML, LVDS Input 5 CLKB LVPECL, CML, LVDS Input 6 VTB − 7 CLKB LVPECL, ...
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Table 5. ATTRIBUTES Input Default State Resistors ESD Protection Moisture Sensitivity (Note 2) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Table 6. MAXIMUM RATINGS Symbol Parameter ...
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Table 7. DC CHARACTERISTICS, CLOCK Inputs, LVPECL Outputs V = 2.375 −40°C to +85°C (Note Symbol Characteristic I Power Supply Current (Inputs and Outputs Open) EE ...
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Table 8. AC CHARACTERISTICS V Symbol Characteristic fin Maximum Input CLOCK Frequency max V Output Voltage Amplitude (@ V OUTPP (See Figure Propagation Delay to CLKx/CLKx to Qx/Qx PLH t Output Differential ÷ 1 PHL trr Reset ...
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... Figure 4. NB4L339 vs. Agilent 8665A 622.08 MHz at 3.3 V, Room Ambient 800 700 600 500 400 300 200 100 0 0 0.1 Figure 5. Output Voltage Amplitude (V Application Information The NB4L339 is a high−speed, Clock multiplexer, divider and low skew fan−out buffer featuring a 2:1 Clock multiplexer front end and outputs a selection of four different divide ratios ...
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MR CLK Q (÷1) Q (÷2) Q (÷4) Q (÷8) CLK MR Q (÷n) NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK, following a high−to−low clock transition. CLK Q (÷n) EN ...
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CLKn 50 W VTn 50 W CLKn Figure 9. Input Structure IHmax V thmax V ILmax Vth CLK IHmin V thmin V ILmin V EE Figure 11. V Diagram th ...
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... Figure 20. Capacitor−Coupled Single−Ended ) Interface (V REFAC http://onsemi.com NB4L339 CLKx LVDS V = OPEN T Driver CLKx CLKx GND GND Figure 17. LVDS Interface V NB4L339 CLKx REFAC 50 W CLKx (open) GND Connected to External V T REFAC ...
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... Figure 21. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices) ORDERING INFORMATION Device NB4L339MNG NB4L339MNR2G *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/ ...
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... D 5.00 BSC D2 2.950 3.100 3.250 E 5.00 BSC E2 2.950 3.100 3.250 e 0.500 BSC K 0.200 −−− −−− L 0.300 0.400 0.500 5.30 3.20 3.20 5. 0.50 PITCH ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB4L339/D ...