NB4L339MNR4G ON Semiconductor, NB4L339MNR4G Datasheet - Page 6

• Manufacturer Part Number: NB4L339MNR4G
• Description: IC CLOCK IN-DIFF LVPECL 32-QFN
• Manufacturer: ON Semiconductor
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of NB4L339MNR4G

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL
• Output: LVPECL
• Frequency - Max: 700MHz
• Voltage - Supply: 2.375 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Frequency-max: 700MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NB4L339MNR4G; NB4L339MNR4GOSTR

NOTE:
9. Measured by forcing V
10. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 50 MHz.
11. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
12. Device to device skew is measured between outputs under identical transition @ 50 MHz.
13. Additive RMS jitter with 50% duty cycle clock signal; all inputs and outputs active.
14. V
Table 8. AC CHARACTERISTICS
Symbol
fin
V
t
t
trr
DCO
t
t
t
t
F
t
t
V
t
PLH
PHL
SKEW
s
h
PW
JIT1
JIT2
r
, t
OUTPP
INPP
N
100 ps (20% − 80%).
the delays are measured from the cross−point of the inputs to the cross−point of the outputs.
max
f
INPP
,
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
(Max) cannot exceed V
Maximum Input CLOCK Frequency
Output Voltage Amplitude (@ V
(See Figure 4)
Propagation Delay to
Output Differential ÷ 1
Reset Recovery
Output CLOCK Duty Cycle
Within Device Skew (Note 11)
Device to Device Skew (Note 12)
Setup Time @ 50 MHz
Hold Time @ 50 MHz
Minimum Pulse Width
Phase Noise
Integrated Phase Jitter (Figure 4)
f
Random Clock Period Jitter (Note 13)
f
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 14)
Output Rise/Fall Times @ 622.08 MHz
input frequency (20% − 80%)
in
in
= 622.08 MHz, 12 kHz − 20 MHz Offset
= 622.08 MHz
INPP
Characteristic
(Min) from a 50% duty cycle clock source. All loading with an external R
CC
− V
CLKx/CLKx to Qx/Qx
Outputs (A) Div by 1
EE
V
. Input voltage swing is a single−ended measurement operating in differential mode.
CC
DIVSEL to CLKx
CLKx to DIVSEL
f
in
INPPmin
CLKSEL to Qx
= 622.08 MHz
f
= 2.375 V to 3.6 V, V
in
EN to CLKx
CLKx to EN
≤ 622 MHz
All Divides
All Divides
All Divides
MR to Qx
)
100 kHz
10 MHz
20 MHz
40 MHz
10 kHz
1 MHz
MR
http://onsemi.com
−100
Min
700
530
900
800
150
0.8
1.2
0.8
4.0
5.0
40
0
EE
6
= 0 V (Note 9)
−40_C
0.15
Typ
730
150
1.0
1.0
0.5
30
90
−
Max
0.25
190
250
1.3
5.0
1.3
1.5
60
60
−100
Min
700
530
900
800
150
0.8
1.2
0.8
4.0
5.0
40
0
25_C
−136
−136
−141
−141
−141
−141
0.15
Typ
730
150
1.0
1.0
0.5
30
90
−
L
Max
0.25
190
250
1.3
5.0
1.3
1.5
60
60
= 50 W to V
−100
Min
700
530
900
800
150
0.8
1.2
0.8
4.0
5.0
40
0
CC
85_C
− 2 V Input edge rates
0.15
Typ
730
150
1.0
1.0
0.5
30
90
−
Max
0.25
190
250
1.3
5.0
1.3
1.5
60
60
RMS
RMS
Unit
MHz
dBc
mV
mV
ns
ns
ps
ps
ps
ns
ps
ps
ps
%