ICS558G-02 IDT, Integrated Device Technology Inc, ICS558G-02 Datasheet - Page 2

• Manufacturer Part Number: ICS558G-02
• Description: IC CLK DVR PECL/CMOS 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: ClockBlocks™r
• Type: Fanout Buffer (Distribution), Dividerr

Specifications of ICS558G-02

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/No
• Input: LVHSTL
• Output: CMOS
• Frequency - Max: 250MHz
• Voltage - Supply: 3.15 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Number Of Outputs: 4
• Operating Supply Voltage (max): 3.5V
• Operating Temp Range: 0C to 70C
• Propagation Delay Time: 12ns
• Operating Supply Voltage (min): 3.15V
• Mounting: Surface Mount
• Pin Count: 16
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSSOP
• Input Frequency: 250MHz
• Duty Cycle: 55%
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency-max: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 558G-02

Pin Assignment
Pin Descriptions
IDT™ / ICS™ LVHSTL TO CMOS CLOCK DIVIDER
ICS558-02
LVHSTL TO CMOS CLOCK DIVIDER
Number
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
HCLK
HCLK
GND
GND
VDD
VDD
OE0
SEL
16 Pin 173 Mil (0.65mm) TSSOP
Name
1
2
3
4
5
6
7
8
HCLK
HCLK
CLK4
CLK3
CLK2
CLK1
GND
GND
GND
VDD
VDD
VDD
VDD
OE0
OE1
SEL
Pin
Output
Output
Output
Output
Power
Power
Power
Power
Power
Power
Power
Type
Input
Input
Input
Input
Input
16
15
14
13
12
11
10
Pin
9
GND
VDD
VDD
CLK1
CLK2
CLK3
CLK4
OE1
Select pin for output divider. See table above. Internal pull-up to VDD.
Connect to +3.3 V.
Connect to +3.3 V.
Differential LVHSTL input (true input).
Differential LVHSTL input (complimentary input).
Connect to ground.
Connect to ground.
Output enable for CLK1 and CLK2. See table above. Internal pull-up
to VDD.
Output enable for CLK3 and CLK4. See table above. Internal pull-up
to VDD.
Connect to ground.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Connect to +3.3 V.
Connect to +3.3 V.
2
Tri-State Table
Output Divide Selection
Pin Description
OE1 OE0 CLK 1, CLK 2
SEL
0
0
1
1
0
1
0
1
0
1
Output Divide
/3
/4
Clock ON
Clock ON
Tri-state
Tri-state
LVHSTL CLOCK DIVIDER
ICS558-02
CLK 3, CLK 4
Clock ON
Clock ON
Tri-state
Tri-state
REV D 020504