TUA 6030 Infineon Technologies, TUA 6030 Datasheet - Page 22

• Manufacturer Part Number: TUA 6030
• Description: IC MIXER/OSC/PLL DIGITAL TSSOP38
• Manufacturer: Infineon Technologies

Specifications of TUA 6030

• Package / Case: 38-TSSOP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Bus Type: I2C
• Maximum Agc: 0.5 dB
• Maximum Frequency: 863.25 MHz
• Minimum Frequency: 44.25 MHz
• Modulation Technique: FM
• Mounting Style: SMD/SMT
• Function: PAL, NTSC
• Noise Figure: 8 dB
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.5 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 10 C
• Maximum Operating Temperature: + 125 C
• Packages: PG-TSSOP-38
• Vs (min): 4.5 V
• Vs (max): 5.5 V
• Icc (max): 66.0 mA
• Esd Protection (max): 2.0 kV
• Mounting: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000012954; TUA6030XT

TUA6030, TUA6032
Functional Description
SCL remains high. All further information transfer takes place during SCL = low,
and the data is forwarded to the control logic on the positive clock edge.
The table ’Bit Allocation’ (
)
see Table 5-4 Bit Allocation Read / Write on page 39
should be referred to for the following description. All telegrams are transmitted
byte-by-byte, followed by a ninth clock pulse, during which the control logic
returns the SDA line to low (acknowledge condition). The first byte is comprised
of seven address bits. These are used by the processor to select the PLL from
several peripheral components (address select). The LSB bit (R/W) determines
whether data are written into (R/W = 0) or read from (R/W = 1) the PLL.
In the data portion of the telegram during a WRITE operation, the MSB bit of the
first or third data byte determines whether a divider ratio or control information
is to follow. In each case the second byte of the same data type has to follow
the first byte. Appropriate setting of the test bits will decide whether the band-
switch byte or the auxiliary byte will be transmitted (
see Table 5-7 Test modes on
).
page 40
If the address byte indicates a READ operation, the PLL generates an acknowl-
edge and then shifts out the status byte onto the SDA line. If the processor gen-
erates an acknowledge, a further status byte is output; otherwise the data line
is released to allow the processor to generate a stop condition. The status word
consists of three bits from the A/D converter, the lock flag and the power-on flag.
Four different chip addresses can be set by an appropriate DC level at pin AS
(
).
see Table 5-6 Address selection on page 40
While the supply voltage is applied, a power-on reset circuit prevents the PLL
from setting the SDA line to low, which would block the bus. The power-on reset
flag POR is set at power-on and if V
falls below 3.2 V. It will be reset at the
CC
end of a READ operation.
Wireless Components
3 - 22
Specification, July 2001