TUA 6030 Infineon Technologies, TUA 6030 Datasheet - Page 21

• Manufacturer Part Number: TUA 6030
• Description: IC MIXER/OSC/PLL DIGITAL TSSOP38
• Manufacturer: Infineon Technologies

Specifications of TUA 6030

• Package / Case: 38-TSSOP
• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Frequency-max: *
• Bus Type: I2C
• Maximum Agc: 0.5 dB
• Maximum Frequency: 863.25 MHz
• Minimum Frequency: 44.25 MHz
• Modulation Technique: FM
• Mounting Style: SMD/SMT
• Function: PAL, NTSC
• Noise Figure: 8 dB
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.5 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 10 C
• Maximum Operating Temperature: + 125 C
• Packages: PG-TSSOP-38
• Vs (min): 4.5 V
• Vs (max): 5.5 V
• Icc (max): 66.0 mA
• Esd Protection (max): 2.0 kV
• Mounting: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000012954; TUA6030XT

Wireless Components
3.4.3
3.4.4
By means of control bit CP the pump current can be switched between two val-
ues by software. This programmability permits alteration of the control response
of the PLL in the locked-in state. In this way different VCO gains can be com-
pensated, for example.
The software controlled ports P0 to P7 are general purpose open-collector out-
puts. The test bits T2, T1, T0 =1, 0, 0 switch the test signals f
signal) and f
The lock detector resets the lock flag FL if the width of the charge pump current
pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, if
FL = 1, the maximum deviation of the input frequency from the programmed fre-
quency is given by
where I
lator frequency and C
charge pump pulses at i.e. 62.5 kHz (= f
to be reset after the loop has lost lock state.
Once FL has been reset, it is set only if the charge pump pulse width is less than
250 ns for eight consecutive f
144 s for FL to be set after the loop regains lock.
AGC
The wide-band AGC stage detects the level of the IF output signal and gener-
ates an AGC voltage for gain control of the tuner input transistors. The AGC
take-over and the time constant are selectable by the I
I
Data is exchanged between the processor and the PLL via the I
clock is generated by the processor (input SCL). Pin SDA functions as an input
or output depending on the direction of the data (open collector, external pull-
up resistor). Both inputs have a hysteresis and a low-pass characteristic, which
enhance the noise immunity of the I
The data from the processor pass through an I
their function the data are subsequently stored in registers. If the bus is free,
both lines will be in the marking state (SDA, SCL are high). Each telegram
begins with the start condition and ends with the stop condition. Start condition:
SDA goes low, while SCL remains high. Stop condition: SDA goes high while
2
C-Bus Interface
P
is the charge pump current, K
ref
(i.e.4 MHz / 64) to P4 and P5 respectively.
f =
1
, C
I
3 - 21
P
2
the capacitances in the loop filter (
(K
VCO
ref
periods. Therefore it takes between 128 and
/ f
XTAL
2
C bus.
VCO
ref
)
), it takes a maximum of 16 s for FL
(C1+C2) / (C1 C2)
the VCO gain, f
2
C bus controller. Depending on
TUA6030, TUA6032
Functional Description
2
C bus.
Specification, July 2001
Xtal
Chapter 4
div
the crystal oscil-
2
(divided input
C bus. The
). As the