BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 39

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IEEE PCS REGISTERS (3.0 TO 3.25/3.0019’H)
Note (1): This bit is not permitted to be a PCS loopback bit by IEEE 802.3ae-2002 subclause 45.2.3.1.2 in 10GBASE-X PCS devices. Intersil has submitted a
Note (1): This bit is latched low on a detected Fault condition. It is set high on being read.
Note (1): Although the 802.3ae specification describes this register as type R/W, this register cannot have any value other than that reflecting the 10GBASE-X PCS.
3.0.15
1.0.15
4.0.15
3.0.14
3.0.13
3.0.12
3.0.11
3.0.10:7
3.0.6
3.0.5:2
3.0.1:0
3.1.15:8
3.1.7
3.1.6:3
3.1.2
3.1.1
3.1.0
3.7.15:2
3.7.1:0
BIT(S)
BIT
(1)
maintenance request (#1113) to allow that use of this bit. Many XENPAK hosts, however, expect this loopback (which is mandatory for 10GBASE-R PCS
devices). Setting the 3.C001’h.7 bit, (Table 64) will activate this loopback enable bit, but cause the BBT3821 to be non-conforming to the current 802.3
specification. See “Loopback Modes ” on page 13).
Thus writing any other value is ignored, and the register is in effect type RO.
BIT
Reserved
Local Fault
Reserved
Rx Link Up
LoPwrAble
Reserved
Reset
PCS_LB_EN
Speed Select
Reserved
LOPOWER
Reserved
Speed Select
Speed Select
Reserved
NAME
Reserved
PCS Type
NAME
NAME
39
1 = PCS Local Fault
1 = PCS Rx Link Up
0 = PCS Rx Link Down
Low Power Ability
1 = reset
0 = reset done, normal
operation
Optionally, enable PCS
Loopback, otherwise
reserved
1 = 10Gbps
0 = Normal Power
1 = 10Gbps
0000 = 10Gbps
01 = 10GBASE-X
SETTING
SETTING
Table 59. IEEE PCS TYPE SELECT REGISTER
Table 57. IEEE PCS CONTROL 1 REGISTER
MDIO REGISTER ADDRESS = 3.0 (3.0000’h)
MDIO REGISTER ADDRESS = 3.1 (3.0001’h)
MDIO REGISTER ADDRESS = 3.7 (3.0007’h)
Table 58. IEEE PCS STATUS 1 REGISTER
SETTING
BBT3821
00’h
0
1
0
0
0’h
DEFAULT
(1)
0’b
0’b
1’b
00’h
0’b
1’b
0’h
0’b
DEFAULT
000’h
01b
DEFAULT
RO
RO LL
RO
R/W SC Writing 1 to this bit will reset the whole chip,
R/W
RO
R/W
RO
RO
R/W
R/W
(1)
RO
including the MDIO registers.
If enabled by EN_PCS_LB (see bit 3.C001’h.7,
Table 64) perform PCS Loopback, and is a R/W bit;
otherwise, effectively a reserved RO 0’b bit
1 = bits 5:2 select speed
No Low Power Mode, writes ignored
1 = bits 5:2 select speed
Operates at 10Gbps
R/W
Derived from Register 3.0008’h
‘Up’ means CX4/LX4 signal level is OK, Byte
Synch and Lane-Lane Alignment have all
occurred
Device does not support a low power mode
(1)
Writes ignored
DESCRIPTION
DESCRIPTION
DESCRIPTION
(1)
.