bbt3821 Intersil Corporation, bbt3821 Datasheet

bbt3821

Manufacturer Part Number

bbt3821

Description

Octal Multi-rate Lx4/cx4 - Xaui Re-timer

Manufacturer

Intersil Corporation

Datasheet

1.BBT3821.pdf (75 pages)

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Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

bbt3821-JH

Manufacturer:

INTERSIL

Quantity:

140

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BOSTOCK HK LIMITED

Part Number:

bbt3821-JH

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Intersil

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Part Number:

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INTERSIL

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Octal 2.488Gbps to 3.187Gbps/

Lane Retimer

Features

• 8 Lanes of Clock & Data Recovery and Retiming; 4 in

• Differential Input/Output

• Wide Operating Data Rate Range: 2.488Gbps to

• Ultra Low-Power Operation (195mW typical per lane,

• Low Power Version Available for LX4 Applications

• 17mm Square Low Profile 192 pin 1.0mm Pitch EBGA

• Compliant to the IEEE 802.3 10GBASE-LX4(WWDM),

• Reset Jitter Domain

• Meets 802.3ae and 802.3ak Jitter Requirements with

• Received Data Aligned to Local Reference Clock for

• Increase Driving Distance

• LX4: Up to 40 inches of FR-4 Traces or 500 Meters of

• CX4: Over 15 meters of Compatible Cable

• Deskewing and Lane-to-Lane Alignment

Egress 3

Each Direction

3.1875Gbps, and 1.244Gbps to 1.59325Gbps

1550mW typical total consumption)

Package

10GBASE-CX4, and XAUI Specifications

Significant Margin

Retransmission

MMF Fiber at 3.1875Gbps

Egress 2

Egress 1

Egress 0

Ingress 3

Ingress 2

Ingress 1

Ingress 0

RX0N

RX0P

RFCP

RFCN

Clock Multiplier

Recovery

Clock &

Data

Data Sheet

3.125G

Deserializer

and Comma

Detector

Figure 1. FUNCTIONAL BLOCK DIAGRAM

MDIO

1-888-INTERSIL or 1-888-352-6832

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

MDC

Decoder

8B/10B

• 0.13mm Pure-Digital CMOS Technology

• 1.5V Core Supply, Control I/O 2.5V Tolerant

• Clock Compensation

• Tx/Rx Rate Matching via IDLE Insertion/Deletion up to

• Receive Signal Detect and 16 Levels of Receiver

• CML CX4 Transmission Output with 16 Settable Levels of

• Single-Ended or Differential Input Lower-Speed Reference

• Ease of Testing

• Complete Suite of Ingress-Egress Loopbacks

• Full 802.3ae Pattern Generation and Test, including

• PRBS (both 2

• JTAG and AC-JTAG Boundary Scan

• Long Run Length (512 bit) Frequency Lock Ideal for

• Extensive Configuration and Status Reporting via 802.3

• Automatic Load of BBT3821 Control and all XENPAK

MDIO/MDC

±100ppm Clock Difference

Equalization for Media Compensation

Pre-Emphasis, Eight on XAUI Side

Clock

CJPAT & CRPAT

Error Flags and Count Output

Proprietary Encoding Schemes

Clause 45 Compliant MDC/MDIO Serial Interface

Registers from EEPROM or DOM Circuit

All other trademarks mentioned are the property of their respective owners.

July 20, 2005

Intersil (and design) is a registered trademark of Intersil Americas Inc.

Receive

FIFO

-1 and 13458 byte) Built-In Self Tests,

Receive

Parallel

Data

C Interface

Encoder

8B/10B

& Mux

BBT3821

FN7483.2

SCL

TX0N

TX0P

SDA

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