SI5013-D-GM Silicon Laboratories Inc, SI5013-D-GM Datasheet - Page 19

• Manufacturer Part Number: SI5013-D-GM
• Description: IC CLOCK/DATA RECOVERY 28MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SI5013-D-GM

• Input: Differential
• Output: CML
• Frequency - Max: 675MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 675MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1277

5. Pin Descriptions: Si5013
Pin #
1
3
4
SLICE_LVL
Pin Name
RATESEL
LOS_LVL
Figure 15. Si5013 Pin Configuration
SLICE_LVL
I/O
Table 8. Si5013 Pin Descriptions
RATESEL
REFCLK+
REFCLK–
LOS_LVL
I
I
I
GND
LOL
1
2
3
4
5
6
7
Signal Level
28 27 26 25 24 23 22
8
LVTTL
9
Rev. 1.6
10 11 12 13 14
GND
Pad
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Notes:
LOS Level Control.
The LOS threshold is set by the input voltage level
applied to this pin. Figure 6 on page 13 shows the
input setting to output threshold mapping.
LOS is disabled when the voltage applied is less
than 1 V.
Slicing Level Control.
The slicing threshold level is set by applying a volt-
age to this pin as described in the Slicing Level sec-
tion of the data sheet. If this pin is tied to GND,
slicing level adjustment is disabled, and the slicing
level is set to the midpoint of the differential input
signal on DIN. Slicing level becomes active when
the voltage applied to the pin is greater than
500 mV.
1. This input has a weak internal pullup.
2. After any change in RATESEL, the device must be
21
20
19
18
17
16
15 TDI
reset.
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
Description
Si5013
19