SY69753LHI TR Micrel Inc, SY69753LHI TR Datasheet - Page 6

• Manufacturer Part Number: SY69753LHI TR
• Description: IC CLOCK/DATA RECVRY 3.3V 32TQFP
• Manufacturer: Micrel Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SY69753LHI TR

• Input: PECL, TTL
• Output: PECL, TTL
• Frequency - Max: 1.25GHz
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP Exposed Pad, 32-eTQFP, 32-HTQFP, 32-VQFP
• Frequency-max: 1.25GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: SY69753LHITR; SY69753LHITR

Functional Block
Functional Description
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The
clock is phase aligned by a PLL so that it samples the
data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency detector. Output
pulses from the detector indicate the required
direction of phase correction. These pulses are
smoothed by an integral loop filter. The output of the
loop filter controls the frequency of the Voltage
Controlled Oscillator (VCO), which generates the
recovered clock.
Frequency stability, without incoming data, is
guaranteed by an alternate reference input (REFCLK)
that the PLL locks onto when data is lost. If the
Frequency of the incoming signal varies by greater
than approximately 1000ppm with respect to the
synthesizer frequency, the PLL will be declared out of
lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal. This transfer function yields a 30µs data
stream of continuous 1's or 0's for random incoming
NRZ data.
December 2007
6
The total loop dynamic of the clock recovery PLL
provides jitter tolerance which is better than the
specified tolerance in GR-253-CORE.
Lock Detect
The SY69753L contains a link fault indication circuit,
which monitors the integrity of the serial data inputs. If
the received serial data fails the frequency test, then
the PLL will be forced to lock to the local reference
clock. This will maintain the correct frequency of the
recovered clock output under loss of signal or loss of
lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by
more than approximately 1000ppm, the PLL will be
declared out of lock. The lock detect circuit will poll the
input data stream in an attempt to reacquire lock to
data. If the recovered clock frequency is determined to
be within approximately 1000ppm, the PLL will be
declared in lock and the lock detect output will go
active.
Performance
The SY69753L PLL complies with the jitter
specifications proposed for SONET/SDH equipment
defined by the Bellcore Specifications: GR-253-
CORE, Issue 2, December 1995 and ITU-T
Recommendations: G.958 document, when used with
differential inputs and outputs.
[e-mail]
or [phone]
M9999-120307-F