SY87739LHG Micrel Inc, SY87739LHG Datasheet - Page 9

• Manufacturer Part Number: SY87739LHG
• Description: IC SYNTHESIZER FRACT 3.3V 32TQFP
• Manufacturer: Micrel Inc
• Type: Fractional Synthesizerr

Specifications of SY87739LHG

• Input: PECL
• Output: PECL
• Frequency - Max: 729MHz
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP Exposed Pad, 32-eTQFP, 32-HTQFP, 32-VQFP
• Frequency-max: 729MHz
• For Use With: 576-1406 - BOARD EVAL N SY87739 EXPERIMENT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1407

Micrel, Inc.
P Divider
down before appearing at the CLKOUT± pins. Notice that,
given the range of the wrapper VCO (540MHz to 729MHz)
and the maximum and minimum division ratios of the P
divider (1 to 60, as shown in Table 5), the minimum and
maximum frequency of CLKOUT± is 10MHz and 729MHz
respectively.
M9999-062807
[e-mail] or [phone]
The output of the wrapper synthesizer is post divided
NdivSel2
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 5. Setting to Program the Division Ratio
0
0
0
0
1
1
1
1
Table 4. NdivSel Divisor Control
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PostDivSel Bit
NdivSel1
of the P Divider
0
0
1
1
0
0
1
1
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
NdivSel0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Divisor
Divisor
16
16
18
17
31
14
32
15
10
11
12
13
14
15
16
18
20
22
24
26
28
30
32
36
40
44
48
52
56
60
1
3
2
3
4
5
6
7
8
9
9
PostDivSel register determines the divisor value. It is set as
per Table 5. The SY87739L does not guarantee a 50%
duty cycle output. It is designed to provide well timed rising
edges only.
MicroWire™ Interface
SY87739L to microcontrollers. The SY87739L accepts one
data bit on PROGDI per rising edge on PROGSK. The data
is ignored when PROGCS is inactive low. When PROGCS
is active high, bits are shifted into the SY87739L. The falling
edge of PROGCS then initiates acquisition of the output
frequency defined by the 32-bit program just loaded into
the SY87739L.
on the same program, PROGCS needs to toggle high then
low.
Programming
frequency:
serial data streaming protocols. Summary programming
information appears in the next section. The SY87739L also
enables Micrel’s SY87721L AnyRate™ CDR to decode
virtually anything within its range of operation, all from a
27.000MHz reference. Details about how to program the
SY87739L in the general case, including derivation of
programs for both the standard protocols and the AnyRate™
application, appear in an applications note.
The divisor value is selected via MicroWire™. The 5-bit
This standard bit-serial interface eases interfacing the
This means that, if the user wishes to re-acquire based
To program the SY87739L to generate a certain
1. Determine the required values of the programming
2. Set PROGCS active high.
3. Shift in each of the 32 bits, as per Table 6. The fields
4. Set PROGCS inactive low.
5. Wait for LOCKED to assert high.
The SY87739L generates exact frequencies for common
PostDivSel
Preamble
MdivSel
NdivSel
parameters, as summarized in Table 6.
are loaded in sequence, from the first row to the last
row. For each multi-bit field, the most significant bit is
shifted in first. Shift the bits in through PROGDI,
clocking them with PROGSK edges.
divsel
qpm1
Field
mfg.
qp
Table 6. Programming Sequence
# Bits
4
5
5
4
3
5
3
3
Section: Gating the P/P-1 Divider
Section: Gating the P/P-1 Divider
always "0000"
always "000"
Reference
Table 1
Table 5
Table 4
Table 3
SY87739L