SY87739LHG Micrel Inc, SY87739LHG Datasheet - Page 8

• Manufacturer Part Number: SY87739LHG
• Description: IC SYNTHESIZER FRACT 3.3V 32TQFP
• Manufacturer: Micrel Inc
• Type: Fractional Synthesizerr

Specifications of SY87739LHG

• Input: PECL
• Output: PECL
• Frequency - Max: 729MHz
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP Exposed Pad, 32-eTQFP, 32-HTQFP, 32-VQFP
• Frequency-max: 729MHz
• For Use With: 576-1406 - BOARD EVAL N SY87739 EXPERIMENT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1407

Micrel, Inc.
the same coarse adjustment voltage, and so both center
nominally at the same frequency.
acquisition sequencer steps through this counter, which
changes its voltage by about 12mV per step. The coarse
input to the VCO is nominally set at 500MHz per Volt.
trim circuit so that the VCO control voltage ends up within
about 12mV of where it should be, were it exactly centered
for the desired output frequency.
Lock Detector
synthesizers by verifying that both PLL have achieved lock.
The LOCKED output asserts active high only when this is
the case, that is, both PLL are locked.
both simple and robust.
provides a charge pump output that is the logical OR of
pump up and pump down pulses.
with a pulse width discriminator. Once each reference clock
rising edge, the discriminator will produce a pulse, only if
the phase difference between the feedback divider and the
reference input is too large.
PLL that is out of lock, is declared to be in lock only if 256
consecutive reference clocks have NO large phase errors,
as reported by the pulse width discriminator. Any large phase
error event, even a single one, that arrives before lock is
declared, will reset the circuit.
phase-difference than small-phase-difference events occur
that is, if over time, a net of 256 large-phase-difference
events occur. That is accomplished by counting up when
large-phase-difference events occur and counting down in
the case of small-phase events.
Wrapper Synthesizer
processed by a more classical PLL circuit, as shown in
Figure 3.
the fractional-N loop. This comes in handy where digital
wrapper and/or FEC is implemented. The wrapper
M9999-062807
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Frequency
An 8-bit counter implements the voltage steps. The
The acquisition sequencer exercises the center frequency
The SY87739L ensures proper operation of both
The SY87739L implements a digital lock detector that is
The lock detect circuit processes this charge pump output
These pulses are subsequently processed digitally. A
Once in lock, a PLL is declared out of lock if more large-
The frequency generated by the fractional-N PLL is further
This circuit further modifies the frequency generated by
(f
FNOUT
Input
)
Figure 3. Wrapper Architecture
M
Frequency
Detector/
Charge
Phase-
Pump
Each phase-frequency detector
Loop Filter
N
VCO
Output
Frequency
(f
WROUT
)
8
synthesizer generates just a few ratios near 1.
of M and N, the dividers, as per:
Wrapper Phase-Frequency Detector
for the charge pump, and also generates delta phase for
the lock detector.
Wrapper Charge Pump
frequency detector into current pulses. Charge pump current
is fixed at about 20µA. An external loop filter integrates
these current pulses into a control voltage.
Wrapper VCO
and operation, so that the center frequency trim circuit can
center both the fractional-N VCO and the wrapper VCO at
about the same frequency.
Wrapper M Divider
the wrapper synthesizer modifies the fractional-N output
frequency. The division ratio is selected via MicroWire™,
as the 3-bit MdivSel register, as per Table 3 .
divisors 14, 15, 16, 17, and 18. The second set consists of
31 and 32. Both M and N must be chosen from the same
set. For example, an N divisor of 31 and an M divisor of 17
results in undefined behavior. The
smaller than
Wrapper N Divider
wrapper synthesizer modifies the fractional-N output
frequency. The division ratio is selected via MicroWire™,
as the 3-bit NdivSel register, as per Table 4.
540MHz
×
f
REF
The wrapper modifies the frequency based on the values
This circuit generates pump up and pump down signals
This circuit converts the pump signals from the phase-
This circuit matches the fractional-N VCO in construction
This circuit forms the denominator of the ratio by which
The divisors are in two sets. The first set consists of the
This circuit forms the numerator of the ratio by which the
MdivSel2
≤
0
0
0
0
1
1
1
1
729MHz
≤
f
WROUT
Table 3. MdivSel Divisor Control
17
14
, that is,
MdivSel1
=
M
N
0
0
1
1
0
0
1
1
×
18
14
f
FNOUT
is not allowed.
MdivSel0
=
M
N
⎛
⎜
⎝
0
1
0
1
0
1
0
1
M
N
×
⎞
⎟
⎠
⎡
⎢
⎢
⎣
ratio must be kept
P –
Q
P–1
Q
Divisor
P–1
SY87739L
+
16
16
18
17
31
14
32
15
Q
P
⎤
⎥
⎥
⎦